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bluecheck

A generic test bench written in Bluespec

bsvtokami

Translates Bluespec SystemVerilog to Kami for use with the coq proof assistant.

connectal

Connectal is a framework for software-driven hardware development.

fluteenclavestagging

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

fpgamake

Generates Makefiles to synthesize, place, and route verilog using Vivado

linear-algebra-speed-tests

Multiple speed tests for basic linear algebra algorithms

piccoloenclavestagging

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

ps-eye-encoder

PlayStation Eye Encoder

riscv-configstring-parser

Flex and Bison parser for RISC-V Configuration Strings from Privileged Spec v1.9

riscv-csrs

Specification and Tools for RISC-V Control and Status Registers

riscv-isa-sim

Spike, a RISC-V ISA Simulator

riscv-semantics

tatsu

竜 TatSu generates Python parsers from grammars in a variation of EBNF

yosys

Yosys Open SYnthesis Suite

z3

The Z3 Theorem Prover