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Name: Pei-ju Hsu

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Pei-ju Hsu's Projects

a-uvm-verification-for-dac-and-adc-model-with-apb-bfm

A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence generates addresses and allows the driver to tell the BFM which slave to choose. Subsequently four monitors and scoreboards record each slave’s test results.

systemverilog-implementation-of-ddr3-controller

The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a predefined DDR3 memory. Successful design verification is achieved via a specialized test bench and connected to provided AHB by a SystemVerilog interface.

verilog-implementation-of-a-32-point-ifft-circuit

A FIFO structure is implemented to hold input and output data. There are 32 pairs of real and imaginary inputs, consisting of 4-bit integer and 24-bit decimal values each. The 32-point IFFT has 5 layers with 32 butterflies each. The device operates with a speed of 200MHz.

verilog-implementation-of-a-64-bit-signed-binary-multiplier-divider-circuit

There are no explicit arithmetic operators used in the design (i.e: +,-). The design is built upon instantiation of a 2-bit adder to achieve 32-bit operation. The 64-bit sequential multiplier and divider share the 32-bit adder when in use.

verilog-implementation-of-facial-comparison-image-matching-with-2-d-256-point-dct-and-correlation

(Capstone Masters Project) Image Matching utilizing fast 1-D 256-point discrete cosine transform (DCT) running at 100MHz. The 256-point DCT has 16 layers with 128 operations each. Images are processed through the Verilog device in 1-D, transposed using a Python script, and processed through the Verilog device again as 2-D. The result is a correlation between two images via Python.

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Pei-ju Hsu's Projects

a-uvm-verification-for-dac-and-adc-model-with-apb-bfm

systemverilog-implementation-of-ddr3-controller

verilog-implementation-of-a-32-point-ifft-circuit

verilog-implementation-of-a-64-bit-signed-binary-multiplier-divider-circuit

verilog-implementation-of-facial-comparison-image-matching-with-2-d-256-point-dct-and-correlation

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