Cannot store type float32 for fusion of bn and relu

[apache]

Cannot store type float32 for fusion of bn and relu

[tqchen]

can you paste a copy of ir after tvm.lower?

[wetliu]

It seems it does not do the compute-inline. But it does get into this line of traverse (nhwc version): https://github.com/dmlc/tvm/blob/master/topi/python/topi/cuda/depthwise_conv2d_map.py#L107

Does the scale shift and relu also has layout to be considered?
// attr [DepthwiseConv2d] storage_scope = "global"
allocate DepthwiseConv2d[float32 * 1 * 64 * 64 * 728]
produce DepthwiseConv2d {
// attr [iter_var(blockIdx.x, , blockIdx.x)] thread_extent = 1024
// attr [Filter.shared] storage_scope = "shared"
allocate Filter.shared[float32 * 3 * 3 * 728 * 1]
produce Filter.shared {
for (ax0, 0, 3) {
for (ax1, 0, 3) {
// attr [iter_var(threadIdx.x, , threadIdx.x)] thread_extent = 728
Filter.shared[((((ax0*3) + ax1)728) + threadIdx.x)] = Filter[(((((blockIdx.x/1024)728) + (ax02184)) + (ax1728)) + threadIdx.x)]
}
}
}
for (i.inner, 0, 2) {
for (j.inner, 0, 2) {
// attr [iter_var(threadIdx.x, , threadIdx.x)] thread_extent = 728
DepthwiseConv2d[(((((((blockIdx.x/1024)*728) + (((blockIdx.x % 1024) % 32)1456)) + (((blockIdx.x % 1024)/32)93184)) + (i.inner46592)) + (j.inner728)) + threadIdx.x)] = 0.000000f
for (di, 0, 3) {
for (dj, 0, 3) {
DepthwiseConv2d[(((((((blockIdx.x/1024)*728) + (((blockIdx.x % 1024) % 32)1456)) + (((blockIdx.x % 1024)/32)93184)) + (i.inner46592)) + (j.inner728)) + threadIdx.x)] = (DepthwiseConv2d[(((((((blockIdx.x/1024)*728) + (((blockIdx.x % 1024) % 32)1456)) + (((blockIdx.x % 1024)/32)93184)) + (i.inner46592)) + (j.inner728)) + threadIdx.x)] + (select(((((((1 - di) - i.inner) <= (((blockIdx.x % 1024)/32)*2)) && ((((blockIdx.x % 1024)/32)*2) < ((65 - di) - i.inner))) && (((1 - dj) - j.inner) <= (((blockIdx.x % 1024) % 32)*2))) && ((((blockIdx.x % 1024) % 32)2) < ((65 - dj) - j.inner))), Input[((((((((((blockIdx.x % 1024) % 32)1456) + (((blockIdx.x % 1024)/32)93184)) + (i.inner46592)) + (j.inner728)) + (((blockIdx.x/1024)728) + threadIdx.x)) + (di46592)) + (dj728)) + -47320)], 0.000000f)Filter.shared[((((((blockIdx.x/1024)728) + threadIdx.x) + (di2184)) + (dj728)) - ((blockIdx.x/1024)728))]))
}
}
}
}
}
produce ScaleShift {
for (c, 0, 64) {
for (i, 0, 64) {
for (j, 0, 728) {
ScaleShift[((((c64) + i)728) + j)] = ((DepthwiseConv2d[((((c64) + i)*728) + j)]*Scale[c]) + Shift[c])
}
}
}
}

[wetliu]

@tqchen The problem is that scale shift supports only NCHW layout. I will add another layout to it. Thank you!

[wetliu]

Unfortunately, the problem remains. Here is the tvm.lower:

// attr [DepthwiseConv2d] storage_scope = "global"
allocate DepthwiseConv2d[float32 * 1 * 64 * 64 * 728]
produce DepthwiseConv2d {
// attr [iter_var(blockIdx.x, , blockIdx.x)] thread_extent = 1024
// attr [Filter.shared] storage_scope = "shared"
allocate Filter.shared[float32 * 3 * 3 * 728 * 1]
produce Filter.shared {
for (ax0, 0, 3) {
for (ax1, 0, 3) {
// attr [iter_var(threadIdx.x, , threadIdx.x)] thread_extent = 728
Filter.shared[((((ax0*3) + ax1)728) + threadIdx.x)] = Filter[(((((blockIdx.x/1024)728) + (ax02184)) + (ax1728)) + threadIdx.x)]
}
}
}
for (i.inner, 0, 2) {
for (j.inner, 0, 2) {
// attr [iter_var(threadIdx.x, , threadIdx.x)] thread_extent = 728
DepthwiseConv2d[(((((((blockIdx.x/1024)*728) + (((blockIdx.x % 1024) % 32)1456)) + (((blockIdx.x % 1024)/32)93184)) + (i.inner46592)) + (j.inner728)) + threadIdx.x)] = 0.000000f
for (di, 0, 3) {
for (dj, 0, 3) {
DepthwiseConv2d[(((((((blockIdx.x/1024)*728) + (((blockIdx.x % 1024) % 32)1456)) + (((blockIdx.x % 1024)/32)93184)) + (i.inner46592)) + (j.inner728)) + threadIdx.x)] = (DepthwiseConv2d[(((((((blockIdx.x/1024)*728) + (((blockIdx.x % 1024) % 32)1456)) + (((blockIdx.x % 1024)/32)93184)) + (i.inner46592)) + (j.inner728)) + threadIdx.x)] + (select(((((((1 - di) - i.inner) <= (((blockIdx.x % 1024)/32)*2)) && ((((blockIdx.x % 1024)/32)*2) < ((65 - di) - i.inner))) && (((1 - dj) - j.inner) <= (((blockIdx.x % 1024) % 32)*2))) && ((((blockIdx.x % 1024) % 32)2) < ((65 - dj) - j.inner))), Input[((((((((((blockIdx.x % 1024) % 32)1456) + (((blockIdx.x % 1024)/32)93184)) + (i.inner46592)) + (j.inner728)) + (((blockIdx.x/1024)728) + threadIdx.x)) + (di46592)) + (dj728)) + -47320)], 0.000000f)Filter.shared[((((((blockIdx.x/1024)728) + threadIdx.x) + (di2184)) + (dj728)) - ((blockIdx.x/1024)728))]))
}
}
}
}
}
produce ScaleShift {
for (i, 0, 64) {
for (j, 0, 64) {
for (c, 0, 728) {
ScaleShift[((((i64) + j)728) + c)] = ((DepthwiseConv2d[((((i64) + j)*728) + c)]*Scale[c]) + Shift[c])
}
}
}
}

Thank you!

[tqchen]

This is because the schedule does not successfully fused the compute into scaleshift, and schedule shift computation becomes CPU computation