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65816_interface_system

Soft Core of 65816 in VHDL

80x86

80186 compatible SystemVerilog CPU core and FPGA reference design

alice5

SPIR-V fragment shader GPU core based on RISC-V

ao486_mister

ao486 port for MiSTer

apple-ii_mister

Apple II+ for MiSTer

arcade-foodfight

FPGA foodfight arcade game in verilog

atari7800_mister

Atari 7800 for MiSTer

attila-sim

axi-bfm

Automatically exported from code.google.com/p/axi-bfm

axi4_bfm

AXI 4 BFM library compatible with the Cadence libraries distributed by Xilinx

bbcmicro_mister

BBC Micro B and Master 128K for MiSTer

biriscv

32-bit Superscalar RISC-V CPU

book

cnn

Alpha Data CNN example ported to SystemVerilog

coco3_mister

Coco3 port to Mister

crash

Cognitive Radio Accelerated with Software and Hardware

croyde-riscv

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

custom_part_data_files

Xilinx PCIe to MIG DDR4 example designs and custom part data files

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

displayport_verilog

A Verilog implementation of DisplayPort protocol for FPGAs

ecc-generator

Automatically exported from code.google.com/p/ecc-generator

fpga-network-stack

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

fx68k

FX68K 68000 cycle accurate SystemVerilog core

gba_mister

GBA for MiSTer

gplgpu

GPL v3 2D/3D graphics engine in verilog

hlx_examples

Open Source HLx Examples

ht1080z_mister

port of HT1080Z to MiSTer (Tandy TRS-80 Model I)

hw

RTL, Cmodel, and testbench for NVDLA

macplus_mister

Macintosh Plus for MiSTer

macsehw

Macintosh SE Hardware Designs