Comments (2)
build
is not part of this repository. It was a script and its primary purpose was for designs that used Bluespec's host-to-FPGA communication mechanisms (BlueNoC and SceMi via BlueNoC). That mechanism was built using BSC: Bluespec provided BSV files and pre-generated IP for the FPGA side and C/C++ files for the host side, and the build
script knew where to find those specific files and compile them and synthesize an FPGA bitfile. None of those files have been included in this repo and so the build
script hasn't been included either.
My understanding is that the 6.375 labs don't use Bluespec's communication mechanism but instead use the Connectal mechanism (which has its own FPGA-side and host-side files). This shouldn't require the build
script.
from bsc.
Yes, you are correct. The recent version of the course uses Connectal as the interface mechanism. However the previous offerings did use Bluespec's interface mechanism.
Thanks anyway.
from bsc.
Related Issues (20)
- Internal Compiler Error when quoting a character value. HOT 4
- Bluesim's symbol-probing interface has wrong values for FIFO
- Unresolved numeric contexts that should be resolvable HOT 6
- Verilog import fails in macro substitution HOT 2
- Unexpected syntax error HOT 1
- expandPorts.tcl has hardcoded paths which do not exist. HOT 1
- Unexpected behavior in Stmt sequence when using par HOT 2
- Bluesim divide-by-zero behavior is inconsistent on arm64 HOT 2
- Type synonyms with phantom parameters can lead to strange behaviors (E.g., compiler hang) HOT 4
- doc example for mkUniqueWrapper2 HOT 7
- -remove-unused-modules flag doesn't work with mkProbe module provided in std library HOT 2
- Failures with compilation on raspberry-pi 5 HOT 4
- GCC 14 emits extra warnings HOT 1
- Github's macos-11 runner is going away HOT 1
- [Bluesim] Simulation executable fails with `undefined symbol: _Z21vcd_write_scope_startP9tSimStatePKc` HOT 9
- `sqrtFP` is incorrect HOT 6
- compile to verilog, convert function to function, but not to modules. HOT 1
- Preserving structure at synthesis boundaries HOT 2
- Better control of wrapper generation HOT 6
- Incremental compilation model and UX improvements
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from bsc.