Comments (2)
I've only looked at the top.route file a little bit and it does seem to have a lot of the information that we would need from the netlist. We would need to write an entirely new design query interface for the file, and it would be a lot more work than our Vivado and RapidWright interfaces as there are a lot of built-in commands that make getting the information we need much easier. Jackson and I would need to do more research into the F4PGA flow in order to figure out what kind of design querying support it has, so an interface for this file would likely be a future project.
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My suggestion would be to probably look at the FPGA Interchange format which has a Python API library and integration with RapidWright and Vivado already. The F4PGA tools are slowly moving to producing and consuming this file format.
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Related Issues (20)
- Provide a simple HDL example HOT 1
- Provide support for .ll and essential bits file parsing HOT 1
- Provide test script to test installation
- Same inputs yield different results when the tool is run twice HOT 1
- Provide more clear API for determining resource used by bit HOT 1
- Extend support to HCLK and RIO Tiles HOT 1
- Allow scripts to be run in any directory HOT 1
- Update VivadoQuery handling of GND and VCC nets HOT 1
- Include more specific details in the fault report for some bits HOT 1
- Support Net Tracing to identify PIPs and corresponding bits HOT 1
- Full design sensitivity estimation
- xc7a35t not supported HOT 2
- CLB LUT Fault Modeling HOT 1
- TMR Sensitivity Analysis
- Extend Support to Ultrascale and Ultrascale+ Architectures
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- Switch VivadoQuery TCL interface to use TelNet instead of python subprocesses
- Support UltraScale devices HOT 1
- Review related works
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from bfat.