Chang de's Projects
Config files for my GitHub profile.
As the title says, this is a final topic for DSCP, mainly using python to implement stock analysis.
A comprehensive roadmap for aspiring Embedded Systems Engineers, featuring a curated list of learning resources.
Record the code of Verilog in HDLbits
This is a final project for computer network@NTNU2023, The main purpose is to visualize multiple information so that you can better understand the network situation for obstacle investigation and management.
用於產生Pspice註解的工具,為了電子學實驗報告寫的。
使用Lua+Solar2D開發,根據PVZ遊戲方式打造,角色為NKNU SE的成員們
人聲合成