Chisel v6.0.0 compile works, test fails

[gonsolo]

Chisel v6.0.0 compile works, test fails

[seldridge]

Hi all. Sorry about the breakages with ChiselTest. ChiselTest, from the perspective of the Chisel developers, was not intended to be used beyond Chisel 3.6. ChiselSim was built as a lightweight, maintained replacement in Chisel 5. Please migrate to ChiselSim. More information about the background of this issue and a migration guide is now provided here: http://www.chisel-lang.org/docs/appendix/migrating-from-chiseltest.

If there are features you want/need with ChiselSim (e.g., enqueueSeq/dequeueSeq or fork/join), please open issues or consider contributing these features to the project.

The chipsalliance/chisel-template has been migrated to use ChiselSim.

[gonsolo]

chiseltest sbt publishLocal needs the following patch:

diff --git a/src/main/scala/treadle2/stage/phases/GetFirrtlAst.scala b/src/main/scala/treadle2/stage/phases/GetFirrtlAst.scala
index 388846a..ed856f9 100644
--- a/src/main/scala/treadle2/stage/phases/GetFirrtlAst.scala
+++ b/src/main/scala/treadle2/stage/phases/GetFirrtlAst.scala
@@ -38,7 +38,7 @@ object GetFirrtlAst extends Phase {
     def handleFirrtlFile(): Option[AnnotationSeq] = {
       annotationSeq.collectFirst { case FirrtlFileAnnotation(fileName) => fileName } match {
         case Some(fileName) =>
-          val file = io.Source.fromFile(fileName)
+          val file = scala.io.Source.fromFile(fileName)
           val text = file.mkString
           file.close()

firrtl2 needs the following patch:

diff --git a/build.sbt b/build.sbt
index 895191b0..ffe0d80c 100644
--- a/build.sbt
+++ b/build.sbt
@@ -4,7 +4,7 @@ enablePlugins(SiteScaladocPlugin)
 
 lazy val commonSettings = Seq(
   organization := "edu.berkeley.cs",
-  scalaVersion := "3.2.2",
+  scalaVersion := "2.13.12",
   crossScalaVersions := Seq("2.13.10", "3.2.2")
 )
 
@@ -100,8 +100,7 @@ lazy val docSettings = Seq(
   Compile / doc / scalacOptions ++= Seq(
     // ANTLR-generated classes aren't really part of public API and cause
     // errors in ScalaDoc generation
-    "-skip-packages",
-    "firrtl2.antlr",
+    "-skip-packages:firrtl2.antlr",
     "-Xfatal-warnings",
     "-feature",
     "-diagrams",

After that my project fails with:

[info] java.lang.NoClassDefFoundError: chisel3/internal/firrtl/Width

From my point of view this issue is far from completed.
My wishlist:

1. Before releasing a new Chisel version, keep at least chisel-template and chiseltest working. (Alternatively: How are you testing at SiFive and Berkeley?)
2. At least keep chiseltest compiling.
3. Similarly keep firrtl2 compiling.
4. Don't fork an old compiler just.
   4a. Using Scala 3 makes the forked compiler incompatible to the rest of Chisel/chiseltest/...

As for now I'm staying at 5.1.0, and I hope you consider not breaking external projects in the future.

[gonsolo]

It seems chiseltest is not supported anymore and svsim should be used.
Anyway chisel-template (which should be kept up to date) is still using chiseltest.

[jackkoenig]

This is a binary compatibility issue, please see Chisel's versioning policy: https://www.chisel-lang.org/docs/appendix/versioning

Basically, binary compatibility breaks between major versions, so ChiselTest compiled for Chisel 5.x will not work with Chisel 6.x. Kevin has indicated intent to release ChiselTest for Chisel 6: ucb-bar/chiseltest#699.

[kiniry]

Love your comment's wishlist number 1 in particular, @gonsolo....

Releasing Chisel 6 without having any structured means by which to perform assurance is gonzo. CC @schoeberl (Hi Martin!)

[schoeberl]

Hi Joseph (@kiniry), what is your interest in Chisel?

[kiniry]

Hey @schoeberl! Remember me from DTU? We hardly got to talk while I was working there for a year before joining Galois ten years (!) ago.

We have used Chisel at Galois on several Government-funded R&D projects I have run for the past eight years or so, including taping out several interesting ASICs. E.g., we were responsible for the six SoCs (plus OSs, development toolchains, improvements to clang to support RISC-V, and much more) provided by the Government to DARPA SSITH performers, and we simulated those SoCs in AWS for DARPA FETT, for which we built the entire infrastructure.

We are currently using Chisel on the [DARPA AISS[(https://www.darpa.mil/program/automatic-implementation-of-secure-silicon) program, as we are developing a product line of hardware security engines. Thus, I need to be able to automatically generate model-based test benches and verification benches from our RDE (formally-grounded) designs/models.

While we can go from RDE models to SVA-based benches (or, yuck, UVM), I'd rather push toward stronger integration of Chisel-centric assurance in this project, thus my nudge on this issue.