Related Issues (20)
- Module initialization test fails with ChiselSim while worked on chiseltest
- Chisel chokes on using elements of an unbound Aggregate as elements of a Record HOT 2
- Bulk connection emission for <> fails for "input" wires
- asUInt packing inconsistent for Bundles with type parameters HOT 5
- Please make some classes in simulator package public for simulator customization.
- ChiselSim waveforms HOT 4
- API for specifying customized transforms in ChiselStage (and dependencies?) HOT 1
- SVSim fails when pokeing and incrementing clock in loop
- Proposal for Verification IR with reset HOT 2
- Firtool error occurs when looking up parameters from a definition of a Module with reset HOT 1
- Scala version HOT 2
- Missing layer definitions when using Definition and Instance HOT 1
- UInt<1>(0)' must be a Chisel type, not hardware HOT 2
- How to access chisel-generated modules using SystemVerilog interface
- How to get the current simulated clock time? HOT 3
- Wrong memory initialization with ChiselSim HOT 2
- Mill Blackbox Resource Loading Doesn't Work
- 2D-Vec RegInit doesn't initialize HOT 5
- Merge Layer Blocks in Chisel HOT 1
- Path values do not work with multiple instantiation
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from chisel.