choucl Goto Github PK

astronvimconfig

async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

bsv_tutorial_cn

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

casend

Lightweight, Easy-to-use, Encrypted File Transfer Tool

dotfiles

Linux dot files with choucl configurations

drawbot

LINE bot to draw graph

favo-solver

fpga-bram

fpga-breathinglight

fpga-dsp

fpga-set

fpga-sha256

fpga-sorting

fpga-trafficlight

NCKU FPGA course homework 1. Implementing traffic light simulation on PYNQ-Z2

ibex_system_on_pynq

Combine the ibex core with AXI interface of PULP platform

judgeserver

nvim

Neovim configuration of yuyu's

nvim-basic-ide

This is my attempt at a basic stable starting point for a Neovim IDE.

oboe

Oboe Bluespec Out-of-order Engine

onlinejudge

open source online judge based on Vue, Django and Docker.

onlinejudgefe

A multiple pages app built for OnlineJudge

riscv-arm-asm-comparator

Tool for comparing RISC-V and Arm64 assembly code difference with the same program

transformap

Modified version of the TransforMAP model from "TransforMAP: Transformer for Memory Access Prediction" (Pengmiao Zhang, et al.)