Atomic instruction emulation

[cnlohr]

Atomic instruction emulation

[cnlohr]

Is this to be done on an individual instruction basis? I have to admit I don't fully understand the timing on when things are allowed to happen between loads and stores.

[cnlohr]

Can this be done by just having a global flag of "I have a reservation!" and clearing it if there's an interrupt, and reporting failure to sc?

[misterjdrg]

Can this be done by just having a global flag of "I have a reservation!" and clearing it if there's an interrupt, and reporting failure to sc?

Yes, and them implement amo*_[w|d] instructions in terms of lr/sc loops.
From spec:

We provided fetch-and-op style atomic primitives as they scale to highly parallel systems better
than LR/SC or CAS. A simple microarchitecture can implement AMOs using the LR/SC primi-
tives, provided the implementation can guarantee the AMO eventually completes.

[cnlohr]

I don't need to do that. Because it's just one core (or we can control atomicity with an actual semaphore).

[cnlohr]

Second question: No other memory accesses need to obey this, correct? So if I do have a global memory semaphore, it only needs to be used on RV32A?

[cnlohr]

Just pasting this here:

i=1
while [ $i -le 10000 ]
do
  echo "Running 'ls' in the background, iteration $i"
  ls >/dev/null 2>&1 &
  i=$((i + 1))
done