Related Issues (20)
- Verilog translation HOT 1
- Cannot wrap a VerilogModel into a pymtl model for simulation HOT 4
- Shall we support implicit include dependency in verilog importing? HOT 5
- explicit_modulename doesn't work for a very simple verilog import HOT 3
- The order of test matters if this is correct.
- The order of test matters. I think this is a bug
- pymtl does check ".value" for single level Wire/OutPort but doesn't for the second level within message type
- will pymtl be ported to Python3 HOT 3
- Use apt-get install flex-old instead of flex HOT 6
- Is it possible to generate sequential blocks in runtime? HOT 15
- Help with design low-level HDL language
- when use, there is an error list index out of range in metaclasses.py in the floder named model HOT 8
- Failed Installation HOT 1
- Python list slicing translation
- sext(concat()) does not translate
- Slice on fields in bitstruct does not produce valid Verilog
- pymtl doesn't correctly register combinational blocks that write to slices of an OutPort HOT 2
- possible bug in pclib/ifcs/ValRdyBundle.py HOT 3
- a small confusion of other language model support HOT 4
- ASIC flow tutorial link is broken HOT 1
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from pymtl.