Comments (2)
At some point AXI stream support was added to the CMAC cores in Vivado. Must have been after 2018.3. I'm currently using 2020.1, but it works fine on 2019.1 with a small modification to the CMAC interface to the transceivers. Simplest solution would be to use a newer version of Vivado, but the AXIS-LBUS wrappers are pure verilog, so presumably it would be possible to back-port those separately.
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I see. Thanks for the tip. Let me try to use a wrapper for that purpose. otherwise, a newer version would be a time-saving method to build the project.
Thanks.
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Related Issues (20)
- Tools for AXI Lite register reads/writes and AXI streaming read/writes HOT 21
- An erro during generating project at file "./config.tcl" line 240: ERROR: [Ipptcl 7-29] Invalid param '03f'. HOT 4
- kernel driver license stated ambigiously HOT 3
- Why is distributed RAM used to store packages on the chip, and why is it divided into segment?
- Missing prerequisite in makefile HOT 1
- Document needs to be updated
- Custom App Ports HOT 2
- Cocotb with icarus verilog gets frozen stuck at some point during simulation: How to debug? HOT 2
- port to zc706 HOT 1
- insmod mqnic.ko error HOT 2
- Does corundum support two devices in a server? HOT 3
- Accelerating PPPOE
- petalinux compile error for mqnic module HOT 8
- nic
- Error "Device needs to be reset" when insmod mqnic.ko HOT 1
- AU50 working with DAC but not Optical HOT 3
- issues in doc HOT 1
- Porting PCIe example to zu7cg HOT 7
- mqnic is not compilent from modern kernel HOT 1
- Weird bugs meet with fb2CG and Vivado 2023.2 HOT 3
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