PCIe CORE Parameter AXIS_DATAWIDTH = 64 breaks the design.

[corundum]

PCIe CORE Parameter AXIS_DATAWIDTH = 64 breaks the design.

[alexforencich]

Presumably you mean AXIS_PCIE_DATA_WIDTH? Why would you want to set that to 64?

Currently, CPL_SIZE is 32, so SEG_DATA_WIDTH*SEG_COUNT must be at least CPL_SIZE*8 (256), so AXIS_PCIE_DATA_WIDTH must be at least half of that (128). Now, there should be an assert that triggers, but perhaps it is failing earlier than that due to the parameter values.

If you really need such a narrow setting for AXIS_PCIE_DATA_WIDTH, then what you should do is set it to 128 and drop the clock speed to 125. I think all of the relevant PCIe core configurations support that. At some point, I can look in to adjusting things to remove that restriction, but as most of the targets are running 256 bit or 512 bit interfaces, it's not a high priority.

[kaoruzhu1]

yes, it's not urgent.

I think G2x4 is a reasonable PCIe setting for 10g ETH.

It's expected that a design with 64bX250MHz bus setting has better performance than that with 128bX125MHz.

[alexforencich]

64 bit at 250 MHz is probably also going to be lower resource consumption than 128 bit at 125 MHz. What is your use case for that?

The issue is really on the completion handling side of things; I'm probably going to revisit that relatively soon and I will keep this issue in mind when working on it to see if I can come up with something more reasonable that will work for a 64 bit PCIe interface.