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turbo8051

turbo 8051

ustcrvsoc

一个用 SystemVerilog 编写的，RISC-V 架构的 CPU + SoC

uvm

UVM examples and projects

uvm_auto

uvm auto generator

uvm_axi

uvm AXI BFM(bus functional model)

uvm_candy_lover

:candy:UVM candy lover testbench which uses YASA as simulation script

uvmprimer

Contains the code examples from The UVM Primer Book sorted by chapters.

uvmreference

Reference examples and short projects using UVM Methodology

verification_digital_systems

Verification of Digital Systems (EE382M)

verilog-template

vim-verilog-instance

verilog_instance.vim: create instantiation of ports from port declaration

vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

wujian100_open

IC design and development should be faster，simpler and more reliable

yasa

YASA (Yet Another Spindle Algorithm) : fast and robust detection of spindles, slow-waves, and REMs from sleep EEG recordings.

yasa-1

:snail:Yet Another Simulation Architecture

zynqbook

基于Xilinx Zynq 嵌入式软硬件协同设计实战指南