Comments (4)
You’re summary is correct, yes.
I considered handling this delay explicitly inside each component, but it seems to me that this is not possible for more complex circuits without rewriting the way Circuit ticks.
This would be my first suggestion. Essentially, in each component’s Process_(), set the output(s) from the result(s) of the previous Process_().
Do you have an example of a complex circuit where this wouldn’t work?
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Thanks for getting back to me so quickly!
I am specifically thinking about a circular dependence like this one:
--------------- -------------
| FIFO | | CONSUMER |
| output: data | ---> | input: data |
| input: pop | <--- | output: pop |
---------------- -------------
If I add an internal delay as we discuss above, it basically boils down to structuring the Process_
method in each of the components like this:
void Process_(SignalBus const & inputs, SignalBus& outputs){
// Update output bus based on whatever we calculated last tick
propagate(outputs);
// Execute the actual logic of this component,
// output goes into the internal buffer,
// will be propagated next tick
logic(inputs);
}
Now I think I run into trouble with execution order, because I am forcing the two steps to be executed directly after each other for a given component.
The circuit ticks will end up doing more or less this (pseudocode):
for(auto component: components) {
component.propagate();
component.logic();
}
When in reality, I would need this:
for(auto component: components) {
component.propagate();
}
for(auto component: components) {
component.logic();
}
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One way around this dilemma would be to call propagate
only on even ticks and logic
on odd ticks. That would make sure that correct ordering is conserved. Only hurdle is that it requires signal states to be persistent between ticks. Currently, the signals are being cleared here, here and possibly elsewhere. @MarcusTomlinson would you be open to having this behavior made configurable? Being able to disable the automatic clearing should suffice.
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@MarcusTomlinson would you be open to having this behavior made configurable? Being able to disable the automatic clearing should suffice.
Sure, sounds fair. Could you PR this?
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Related Issues (20)
- sort out git version tags HOT 1
- Crash the program HOT 1
- feature request HOT 3
- [Plugin Load] How do we distinguish between debug and release libraries? HOT 2
- Can a component output be wired to multiple component inputs? HOT 2
- is there a way to define parameters for a component? HOT 5
- spurious auto-ticking when pipeline depth is greater than one but ticking manually HOT 3
- Suggest renaming ReleaseThread() to ReleaseNextThread() HOT 1
- Error when building HOT 2
- Does the project's flow graph support subgraphs? HOT 2
- Async data/event HOT 6
- The Signal.h file is missing, resulting in an error in compiling the Inout project HOT 1
- SocketIn.cpp(26,1): error C2059: syntax error: "}" HOT 1
- aec and agc, Compile Error HOT 2
- Is there any way to get whether the operation of circuit->Tick() is completed? HOT 2
- Is the data structure used in this project DAG? HOT 2
- Why does multithreading get stuck? The program cannot continue to run HOT 7
- Can you add a function interface to save the circuit diagram as a graphviz file format?
- Is it possible to add an exception handling method?
- MoveValue without copy constructor HOT 2
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