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api-config-chipsalliance

A Scala library for Context-Dependent Evironments

axe

Consistency checker for memory subsystem traces

barstools

Useful utilities for BAR projects

berkeley-hardfloat

berkeley-softfloat-3

SoftFloat release 3

berkeley-testfloat-3

TestFloat release 3

block-inclusivecache-sifive

boringssl

Mirror of BoringSSL

capstone

Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings.

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chipyard-toolchain-prebuilt

Pre-built riscv-gnu-toolchain binaries. You should most likely only shallow clone this.

chisel-testers

Provides various testers for chisel users

chisel3

Chisel 3: A Modern Hardware Design Language

convolution-visualizer

Convolution visualizations

coremark-workload

FireMarshal workload for CoreMark EEMBC

cryptography

cryptography is a package designed to expose cryptographic primitives and recipes to Python developers.

dsptools

A Library of Chisel3 Tools for Digital Signal Processing

dtc

Device Tree Compiler

emacs

Mirror of GNU Emacs

esp-binutils-gdb

ESP toolchain binutils port

esp-gnu-toolchain

Custom extensions to the RISC-V toolchain for the UCB-BAR ESP project

esp-isa-sim

Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project

esp-tests

Custom extensions to the RISC-V tests for the UCB-BAR ESP project

firesim

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

firrtl

Flexible Intermediate Representation for RTL

firrtl-interpreter

A scala based simulator for circuits described by a LoFirrtl file

gemmini

Berkeley's Systolic Array Generator

gemmini-rocc-tests

Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator

hammer

HAMMER: Highly Agile Masks Made Effortlessly from RTL

hwacha

Microarchitecture implementation of the decoupled vector-fetch accelerator