Comments (8)
UleyeyeUwma
commented on June 7, 2024
Processor [Intel(R) Xeon(R) CPU E5-1650 v3 @ 3.50GHz]
|- PPIN# [82ef7e64ef306c8d]
|- Architecture [Haswell/EP]
|- Vendor ID [GenuineIntel]
|- Microcode [0x00000000]
|- Signature [ 06_3F]
|- Stepping [ 2]
|- Online CPU [ 12/ 12]
|- Base Clock [ 99.776]
|- Frequency (MHz) Ratio
Min 1197.30 < 12 >
Max 3492.11 < 35 >
|- Factory [100.000]
3500 [ 35 ]
|- Performance
|- P-State
TGT 4090.76 < 41 >
|- Turbo Boost [ UNLOCK]
1C 3791.44 < 38 >
2C 3791.44 < 38 >
3C 3591.89 < 36 >
4C 3591.89 < 36 >
5C 3591.89 < 36 >
6C 3591.89 < 36 >
7C 3591.89 < 36 >
8C 3591.89 < 36 >
9C 3591.89 < 36 >
10C 3591.89 < 36 >
11C 3591.89 < 36 >
12C 3591.89 < 36 >
13C 3591.89 < 36 >
14C 3591.89 < 36 >
15C 3591.89 < 36 >
16C 3591.89 < 36 >
|- Uncore [ UNLOCK]
Min 1197.30 < 12 >
Max 1596.39 < 16 >
|- TDP Level < 0:1 >
|- Programmable [ UNLOCK]
|- Configuration [ UNLOCK]
|- Turbo Activation [ UNLOCK]
Nominal 3492.11 [ 35 ]
Level1 3192.79 [ 32 ]
Turbo 4090.76 < 41 >
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [N] AES [Y] AVX/AVX2 [Y/Y]
|- AMX-BF16 [N] AMX-TILE [N] AMX-INT8 [N] AMX-FP16 [N]
|- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N]
|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNNI [N] AVX512-ALG [N]
|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [N] AVX-VNNI-VEX [N] AVX-VNN-INT8 [N] AVX-NE-CONV [N]
|- AVX-IFMA [N] CMPccXADD [N] MOVDIRI [N] MOVDIR64B [N]
|- BMI1/BMI2 [Y/Y] CLWB [N] CLFLUSH [Y] CLFLUSH-OPT [N]
|- CLAC-STAC [N] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- ENQCMD [N] GFNI [N] OSPKE [N] WAITPKG [N]
|- MMX/Ext [Y/N] MON/MWAITX [Y/N] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [N] RDTSCP [Y]
|- SEP [Y] SHA [N] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/N] SSE4.2 [Y]
|- SERIALIZE [N] SYSCALL [Y] RDPID [N] SGX [N]
|- VAES [N] VPCLMULQDQ [N] PREFETCH/W [N] LZCNT [Y]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- APIC Timer Invariance ARAT [Capable]
|- Core Multi-Processing CMP Legacy [Missing]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Direct Cache Access DCA [Capable]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Capable]
|- CPL Qualified Debug Store DS-CPL [Capable]
|- 64-Bit Debug Store DTES64 [Capable]
|- Fast Short REP CMPSB FSRC [Missing]
|- Fast Short REP MOVSB FSRM [Missing]
|- Fast Short REP STOSB FSRS [Missing]
|- Fast Zero-length REP MOVSB FZRM [Missing]
|- Fast-String Operation ERMS [Capable]
|- Fused Multiply Add FMA [Capable]
|- Hardware Feedback Interface HFI [Missing]
|- Hardware Lock Elision HLE [Missing]
|- History Reset HRESET [Missing]
|- Hybrid part processor HYBRID [Missing]
|- Instruction Based Sampling IBS [Missing]
|- Instruction INVPCID INVPCID [Capable]
|- Long Mode 64 bits IA64 | LM [Capable]
|- Linear Address Space Separation LASS [Missing]
|- Linear Address Masking LAM [Missing]
|- LightWeight Profiling LWP [Missing]
|- Machine-Check Architecture MCA [Capable]
|- Memory Protection Extensions MPX [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Capable]
|- Platform Configuration PCONFIG [Missing]
|- Process Context Identifiers PCID [Capable]
|- Perfmon and Debug Capability PDCM [Capable]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Write Data to a Processor Trace Packet PTWRITE [Capable]
|- PREFETCHIT0/1 Instructions PREFETCHI [Missing]
|- Resource Director Technology/PQE RDT-A [Missing]
|- Resource Director Technology/PQM RDT-M [Capable]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Capable]
|- Self-Snoop SS [Capable]
|- Supervisor-Mode Access Prevention SMAP [Missing]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Thread Director TD [Missing]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Capable]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Missing]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Capable]
|- Write Back & Do Not Invalidate Cache WBNOINVD [Missing]
|- Extended xAPIC Support x2APIC [ xAPIC]
|- Execution Disable Bit Support XD-Bit [Capable]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Capable]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [Capable]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [Capable]
|- Speculative Store Bypass Disable SSBD [Capable]
|- Writeback & invalidate the L1 data cache L1D-FLUSH [Capable]
|- Hypervisor - No flush L1D on VM entry L1DFL_VMENTRY_NO [ Unable]
|- Arch - Buffer Overwriting MD-CLEAR [Capable]
|- Arch - No Rogue Data Cache Load RDCL_NO [ Unable]
|- Arch - Enhanced IBRS IBRS_ALL [ Unable]
|- Arch - Return Stack Buffer Alternate RSBA [ Unable]
|- Arch - No Speculative Store Bypass SSB_NO [ Unable]
|- Arch - No Microarchitectural Data Sampling MDS_NO [ Unable]
|- Arch - No TSX Asynchronous Abort TAA_NO [ Unable]
|- Arch - No Page Size Change MCE PSCHANGE_MC_NO [ Unable]
|- Arch - STLB QoS STLB [ Unable]
|- Arch - Functional Safety Island FuSa [ Unable]
|- Arch - RSM in CPL0 only RSM [ Unable]
|- Arch - Split Locked Access Exception SPLA [ Unable]
|- Arch - Snoop Filter QoS Mask SNOOP_FILTER [ Unable]
|- Arch - No Fast Predictive Store Forwarding PSFD [ Unable]
|- Arch - Data Operand Independent Timing Mode DOITM [ Unable]
|- Arch - Not affected by SBDR or SSDP SBDR_SSDP_NO [ Unable]
|- Arch - No Fill Buffer Stale Data Propagator FBSDP_NO [ Unable]
|- Arch - No Primary Stale Data Propagator PSDP_NO [ Unable]
|- Arch - Overwrite Fill Buffer values FB_CLEAR [ Unable]
|- Arch - Special Register Buffer Data Sampling SRBDS [ Unable]
|- RDRAND and RDSEED mitigation RNGDS [ Unable]
|- Restricted Transactional Memory RTM [ Unable]
|- Verify Segment for Writing instruction VERW [ Unable]
|- Arch - Restricted RSB Alternate RRSBA [ Unable]
|- Arch - No Branch Target Injection BHI_NO [ Unable]
|- Arch - Legacy xAPIC Disable XAPIC_DIS [ Unable]
|- Arch - No Post-Barrier Return Stack Buffer PBRSB_NO [ Unable]
|- Arch - IPRED disabled for CPL3 IPRED_DIS_U [ Unable]
|- Arch - IPRED disabled for CPL0/1/2 IPRED_DIS_S [ Unable]
|- Arch - RRSBA disabled for CPL3 RRSBA_DIS_U [ Unable]
|- Arch - RRSBA disabled for CPL0/1/2 RRSBA_DIS_S [ Unable]
|- Arch - Data Dependent Prefetcher CPL3 DDPD_U_DIS [ Unable]
|- Arch - BHI disabled for CPL0/1/2 BHI_DIS_S [ Unable]
|- No MXCSR Configuration Dependent Timing MCDT_NO [ Unable]
Security Features
|- CPUID Key Locker KL [Missing]
|- AES Key Locker instructions AESKLE [Capable]
|- AES Wide Key Locker instructions WIDE_KL [Capable]
|- Software Guard SGX1 Extensions SGX1 [Missing]
|- Software Guard SGX2 Extensions SGX2 [Missing]
Technologies
|- Data Cache Unit
|- L1 Prefetcher L1 HW < ON>
|- L1 IP Prefetcher L1 HW IP < ON>
|- L2 Prefetcher L2 HW < ON>
|- L2 Line Prefetcher L2 HW CL < ON>
|- System Management Mode SMM-Dual [ ON]
|- Hyper-Threading HTT [ ON]
|- SpeedStep EIST < ON>
|- Dynamic Acceleration IDA [ ON]
|- Turbo Boost TURBO < ON>
|- Energy Efficiency Optimization EEO <OFF>
|- Race To Halt Optimization R2H <OFF>
|- Watchdog Timer TCO <OFF>
|- Virtualization VMX [ ON]
|- I/O MMU VT-d [OFF]
|- Version [ N/A]
|- Hypervisor [OFF]
|- Vendor ID [ N/A]
Performance Monitoring
|- Version PM [ 3]
|- Counters: General Fixed
| { 4, 0, 0 } x 48 bits 3 x 48 bits
|- Enhanced Halt State C1E < ON>
|- C1 Auto Demotion C1A <OFF>
|- C3 Auto Demotion C3A <OFF>
|- C1 UnDemotion C1U <OFF>
|- C3 UnDemotion C3U <OFF>
|- C6 Core Demotion CC6 <OFF>
|- C6 Module Demotion MC6 <OFF>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Hardware Duty Cycling HDC [OFF]
|- Package C-States
|- Configuration Control CONFIG [ LOCK]
|- Lowest C-State LIMIT < C6>
|- I/O MWAIT Redirection IOMWAIT < Enable>
|- Max C-State Inclusion RANGE < C6>
|- Core C-States
|- C-States Base Address BAR [ 0x414 ]
|- ACPI Processor C-States _CST [ 2]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 0 2 1 2 0 0 0 0
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Last Level Cache Misses [Capable]
|- Branch Instructions Retired [Capable]
|- Branch Mispredicts Retired [Capable]
|- Top-down slots Counter [Capable]
|- Processor Performance Control _PCT [ Enable]
|- Performance Supported States _PSS [ 0]
|- Performance Present Capabilities _PPC [ 0]
Power, Current & Thermal
|- Temperature Offset:Junction TjMax < 0: 95 C>
|- Clock Modulation ODCM <Disable>
|- DutyCycle [ 0.00%]
|- Power Management PWR MGMT [ LOCK]
|- Energy Policy Bias Hint < 6>
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Capable]
|- Package Thermal Management PTM [Capable]
|- Thermal Monitor 1 TM1 [ Enable]
|- Thermal Monitor 2 TM2 [Capable]
|- Thermal Design Power TDP [ 140 W]
|- Minimum Power Min [ 47 W]
|- Maximum Power Max [Missing]
|- Thermal Design Power Package [ Enable]
|- Power Limit PL1 [ 140 W]
|- Time Window TW1 [ 1 s]
|- Power Limit PL2 [ 168 W]
|- Time Window TW2 [ 7 ms]
|- Thermal Design Power Core <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power Uncore [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 976 us]
|- Thermal Design Power DRAM <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power Platform [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 976 us]
|- Power Limit PL2 [ 0 W]
|- Time Window TW2 [ 976 us]
|- Electrical Design Current EDC [Missing]
|- Thermal Design Current TDC [Missing]
|- Core Thermal Point
|- DTS Threshold #1 Threshold [Missing]
|- DTS Threshold #2 Threshold [Missing]
|- Package Thermal Point
|- DTS Threshold #1 Threshold [Missing]
|- DTS Threshold #2 Threshold [Missing]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000061035]
|- Window second [ 0.000976562]
CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive
# ID ID ID ID L1-Inst Way L1-Data Way L2 Way L3 Way
000:BSP 0 0 0 32768 8 32768 8 262144 8 15728640 20 i
001: 0 2 1 0 32768 8 32768 8 262144 8 15728640 20 i
002: 0 4 2 0 32768 8 32768 8 262144 8 15728640 20 i
003: 0 6 3 0 32768 8 32768 8 262144 8 15728640 20 i
004: 0 8 4 0 32768 8 32768 8 262144 8 15728640 20 i
005: 0 10 5 0 32768 8 32768 8 262144 8 15728640 20 i
006: 0 1 0 1 32768 8 32768 8 262144 8 15728640 20 i
007: 0 3 1 1 32768 8 32768 8 262144 8 15728640 20 i
008: 0 5 2 1 32768 8 32768 8 262144 8 15728640 20 i
009: 0 7 3 1 32768 8 32768 8 262144 8 15728640 20 i
010: 0 9 4 1 32768 8 32768 8 262144 8 15728640 20 i
011: 0 11 5 1 32768 8 32768 8 262144 8 15728640 20 i
[ 0] American Megatrends Inc.
[ 1] 5.11
[ 2] 10/17/2022
[ 3] Default string
[ 4] Default string
[ 5] Default string
[ 6] D---u---s---n-
[ 7] Default string
[ 8] Default string
[ 9] INTEL
[10] X99
[11] V1.0
[12] M---0---0---0--
[13] Number Of Devices:4\Maximum Capacity:268435456 kilobytes
[14] DIMM_A1\NODE 1
[15]
[16] DIMM_C1\NODE 1
[17]
[18] Undefined
[19]
[20] Undefined
[21]
[22] atermiter
[23]
[24] atermiter
[25]
Linux:
|- Release [6.7.5-arch1-1]
|- Version [#1 SMP PREEMPT_DYNAMIC Sat, 17 Feb 2024 14:02:33 +0000]
|- Machine [x86_64]
Memory:
|- Total RAM 32783608 KB
|- Shared RAM 124064 KB
|- Free RAM 27579944 KB
|- Buffer RAM 3168 KB
|- Total High 0 KB
|- Free High 0 KB
Clock Source < corefreq_tsc>
CPU-Freq driver [ corefreqk-perf]
Governor [ corefreq-policy]
CPU-Idle driver [ corefreqk-idle]
|- Idle Limit < C6>
|- State POLL C1 C1E C3 C6 C7 C8 C9
|- CPUIDLE HSW-C1 HSW-C1E HSW-C3 HSW-C6 HSW-C7 HSW-C8 HSW-C9
|- Power -1 0 0 0 0 0 0 0
|- Latency 0 2 10 33 133 166 300 600
|- Residency 0 2 20 100 400 500 900 1800
Here is the output of corefreq-cli -s -n -m -n -B -n -k
from corefreq.
cyring
commented on June 7, 2024
- Do you confirm you have changed ratio for all Cores ?
I mean did you make sure to select line1C
- Are the MSR really unlocked ?
Let's start with the MSR_TURBO_RATIO_LIMIT (0x1ad)
You can alter register for one frequency ratio using the MSR-Tools
rdmsr -ax 0x1ad
2424242424242626
...
2424242424242626
Now add +1 to 26 and write the register for all Cores
wrmsr -a 0x1ad 0x2424242424242627
Read again the register to check if value is written. If not MSR is locked.
rdmsr -ax 0x1ad
2424242424242627
...
2424242424242627
If value has been successfully altered then you should see a TB ratio of 39 in CoreFreq. (press star key * to force refresh the UI)
At this point let me know how does it work ?
from corefreq.
UleyeyeUwma
commented on June 7, 2024
- Yes.
- The values do not change after applying them and corefreq does not see an increase to 39 (stays at 38).
from corefreq.
cyring
commented on June 7, 2024
Is the processor really unlocked ?
Is there any BIOS option which prevent to alter MSR ?
That option could be named semaphore.
from corefreq.
cyring
commented on June 7, 2024
In this Reddit it shows a BIOS screenshot where ratio all cores can be changed.
Can you change ratio in BIOS and see if CoreFreq reads the same afterwards
from corefreq.
cyring
commented on June 7, 2024
Set individually every Core Ratio Limit to max value, example 38
Source: level1techs.com
Ratios OC seems to be a Xeon bug.
My understanding is that when set to your max ratio in BIOS rather than AUTO then you can increase value from kernel, either CoreFreq either MSR Tools
EDIT: Microcode which is fixing that bug has to be removed from the boot path.
You are using ArchLinux and you can get ride of it in boot loader configuration.
from corefreq.
cyring
commented on June 7, 2024
I had implemented some Memory Controller decoders for Haswell; can you take a screenshot or post corefreq-cli -M ?
Thanks
from corefreq.
UleyeyeUwma
commented on June 7, 2024
Is the processor really unlocked ?
Is there any BIOS option which prevent to alter MSR ? That option could be named semaphore.
Yes the processor is unlocked, however as you probably already figured out, it might've been the bios locking it, I read that message and experimented with different motherboards that I had around (all chinese x99, specifically huananzhi 8m and kllisre v205) and they both seem to be locking it.
Can you change ratio in BIOS and see if CoreFreq reads the same afterwards
There is no such option in the default bios for these motherboards, there are modified bios that implement it but on the B85 Chipset BIOS OC is not allowed and I am unsure what chipset the other motherboard has.
As such I will close this issue as I suspect the issue is due to the motherboard chipset limitations and not related to this program at all.
from corefreq.
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from corefreq.