Fix memory watchpoints

[daniel5151]

Fix memory watchpoints

[daniel5151]

I think I've figured out why I wasn't able to get it working.

TL;DR: The T05;watch:<addr>;... signal must be sent when after the CPU tries to access the memory location, but before it modifies it!

I figured this out by running a local gdbstub+gdb session on my x86 box with set debug remote 1. Here's the transcript:

Sending packet: $Z0,7ffff7fe63e4,1#e6...Packet received: OK
Sending packet: $Z2,7fffffffdbac,4#a3...Packet received: OK
Sending packet: $vCont;c:p5104.-1#a8...Packet received: T05watch:00007fffffffdbac;06:b0dbffffff7f0000;07:b0dbffffff7f0000;10:3f51555555550000;thread:p5104.5104;core:4;
Sending packet: $m7fffffffdbac,4#58...Packet received: 00000000
Sending packet: $m7fffffffdbac,4#58...Packet received: 00000000
Sending packet: $m7fffffffdbac,4#58...Packet received: 00000000
Sending packet: $vCont;c:p5104.-1#a8...Packet received: T05watch:00007fffffffdbac;06:b0dbffffff7f0000;07:b0dbffffff7f0000;10:4d51555555550000;thread:p5104.5104;core:4;
Sending packet: $m7fffffffdbac,4#58...Packet received: 02000000
Sending packet: $qXfer:threads:read::0,1000#92...Packet received: l<threads>\n<thread id="p5104.5104" core="4" name="test"/>\n</threads>\n
Sending packet: $z0,7ffff7fd37a5,1#03...Packet received: OK
Sending packet: $z0,7ffff7fe508e,1#06...Packet received: OK
Sending packet: $z0,7ffff7fe63e4,1#06...Packet received: OK
Sending packet: $z2,7fffffffdbac,4#c3...Packet received: OK

As you can see, the first thing gdb does after receiving the stop signal is to read the value of the memory location. It proceeds to resume execution, and immediately hits the watchpoint again, except this time, when it goes to read the memory location, there's a new value present!

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Unlike my previous mental model (where the only thing that's required is to log when a system has already accessed a memory location), implementing this feature may be tricky depending on how the end user has architected their emulator.

As such, I think the best way to fix this is to extract the log_mem_access callback from the step method, and create a new optional trait method like fn update_hw_breakpoint(&mut self, addr: Self::Usize, op: HwBreakOp) -> Option<Result<(), ()>>) which gives individual targets an option to implement this hardware-level break/watchpoint support.

I'm currently working on a POC, and might push up some work soon-ish.

[daniel5151]

guh, it turns out the real issue was a lot simpler:

• I was writing the target's pc instead of the data address in the Stop packet
• I was using to_ne_bytes instead of to_be_bytes

🤦‍♂️