QMTECH_XC7A100T_Wukong_Board
Board definition files and initial example programs
Github Link
2nd revision board, original data from https://github.com/ChinaQMTECH/XC7A100T-200T_Wukong_Board
Manual
Schematic
A set of board definition files are available which enable board automation. a tcl script to recreate an semi automated design are here:
block design
1
2
3
4
5
6
7
8
9
D2
D3
CMD
VDD
CLK
VSS
D0
D1
CD
H6
J6
L4
3v3
J8
Gnd
M5
M7
N6
6
5
4
3
2
1
3V3
Gnd
G8
G7
G5
D5
3V3
Gnd
G6
D6
E6
E5
12
11
10
9
8
7
6
5
4
3
2
1
3V3
Gnd
A5
A4
F4
H4
3V3
Gnd
B5
B4
G4
J4
12
11
10
9
8
7
1
3
5
7
9
11
13
15
17
3V3
H21
K21
H26
G25
G20
F23
E26
E25
Gnd
H22
J21
G26
F25
G21
E23
D26
D25
2
4
6
8
!0
12
14
16
18
Addon boards (originally built for ebaz)
1
3
5
7
9
11
13
15
17
3V3
SCL
VS
PLK
D7
D5
D3
D1
RST
Gnd
SDA
HS
XLK
D6
D4
D2
D0
PWDN
2
4
6
8
!0
12
14
16
18
6
5
4
3
2
1
3V3
Gnd
F23
E23
E26
D26
3V3
Gnd
G25
F25
G20
G21
12
11
10
9
8
7
6
5
4
3
2
1
3V3
Gnd
G26
H26
H22
H21
Micro SD add-on connections
3V3
Gnd
SCLK
CS
MOSI
MISO
3V3
Gnd
H21
H22
H26
G26
PS/2 keyboard on pmod a bottom row
12
11
10
9
8
7
3V3
Gnd
G6
D6
n/c
n/c
Vcc
Gnd
Data
Clock
Mauve
Blue
Grey
White
1
2
3
4
Test01_led_key
Test04-DDR3_MIG
Test05_usb_uart_cp2102
Test06_HDMI_OUT
Test08_GMII_Ethernet
Litex configuration files
Litex board files suitable for revision 2.0 of the Wukong board, copy into Litex-boards directories
platform
target
Build instructions with Vivado
source /opt/Xilinx/Vivado/2020.2/settings64.sh
cd /home/david/litex-boards/litex_boards/targets/build/qmtech_wukong
export PATH=$PATH:$(echo $PWD/riscv64-*/bin/)
./qmtech_wukong.py --with-sdcard --with-ethernet --with-video-terminal --build --load
/home/david/litex-boards/litex_boards/platforms/qmtech_wukong.py
change constraints for later wukong board
add sdcard pins
add ps/2 keyboard from digilent board
/home/david/litex-boards/litex_boards/targets/qmtech_wukong.py
add sdcard
change DVI resolution
/home/david/litex/litex/soc/software/bios/boot.c
change local and remote ip
/home/david/litex/litex/soc/software/bios/main.c
try adding add some whitespace before boot logo to suppress logo corruption
FPGA-Mandelbrot
Artix-7 Arty Base Project
Video 1
Video 2
Doxygen
Github
Xilinx & RTL8211EG example
TCP/IP stack in SystemVerilog by hypernyan
a TCP stack document
a TCP stack implementation
RTL8211EG data
Gigabit ethernet 1
Gigabit ethernet 2
Board definition used to create block design for hardware export to Vitis.