Erroneous clock frequency

[devttys0]

Erroneous clock frequency

[l29ah]

Check that your logic analyzer measures periods correctly. I had similar problems with another FX2-based LA that lied to me.

[andreireanu]

Thanks for the reply! The thing is I used a different library at some point (pyftdi) and the real frequency was recorded correctly by the analyser, so I don't think there's an issue with it.

[l29ah]

Oh, interesting. By the way, on your screenshot i observe clock blanks being twice as long as the pulses; is it the same with pyftdi?

[andreireanu]

Nope, the blanks were the same size as the ones.

[andreireanu]

I seem to have found the problem:

To make I2C working, FTDI needs to enable what they call a "3 phase clock". PyFtdi implements this feature. The issue with this mode is that it requires 3 clock phase for each clock period, hence the 2:3 ratio. PyFtdi hides this setting from the user, and silently tweaks the specified clock to match what the users expects. libmpsse seems not to do it.

Is anyone aware of the inner working of the libmpsse library and how I could make this change to it? Thanks!

[l29ah]

On Thu, Apr 09, 2020 at 05:25:21AM -0700, Andrei Ungureanu wrote: Is anyone aware of the inner working of the libmpsse library and how I could make this change to it? Thanks!

Check build_block_buffer()

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[l29ah]

Also i see it being enabled in SetMode().

[andreireanu]

Can you please be more specific on where I can find this part of code? I searched for the definitions of the frequency constants and this led me to the compiled _pylibmpsse.so file.