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dm1998

Config files for my GitHub profile.

hls_set_5

panel_display

In this project I designed an module that can synchronise and transfer our data from an fpga to a screen, through a vga cable. For the project an frequency of 60 Hz and resolution of 640x480 were selected. The project is fully implemented on System Verilog and includes the source file,testbench and an .qpf file for the quartus compilation.

risc-v-vector

Vector processor for RISC-V vector ISA

score_4

At this project I designed a module that can execute the classic board game Score 4.The game is played by two players, who are called to select on which column they want to put theirc checker,on everu round. The main goal of the game is to put 4 straight checkers on a diagonal,row or column.The project is fully implemented on System Verilog. In this project there are included the source file,main testbench,an .qpf file for quartus compilation and an vga module so that we can represent the game on a screen through vga cables.