[RISCV] Error on Lichee PI 4a

[bbonev]

[RISCV] Error on Lichee PI 4a

[bbonev]

Thanks! Here are my RISC-V results so far:

[Dr-Noob]

As always, thanks for your feedback.

RISC-V extensions are indeed a headache sometimes, but this is mainly because my implementation was not initially designed for managing cases like the u extension, which, apparently is an invalid extension but still it is shown in cpuinfo...

It should work after the latest patch. Can you provide also the output of cpufetch --verbose? I'd like to fix the Unknown fields.

[bbonev]

bf89096

9a578d3

# cat /proc/cpuinfo 
processor	: 0
hart		: 0
isa		: rv64imafdcvsu
mmu		: sv39
cpu-freq	: 1.848Ghz
cpu-icache	: 64KB
cpu-dcache	: 64KB
cpu-l2cache	: 1MB
cpu-tlb		: 1024 4-ways
cpu-cacheline	: 64Bytes
cpu-vector	: 0.7.1

processor	: 1
hart		: 1
isa		: rv64imafdcvsu
mmu		: sv39
cpu-freq	: 1.848Ghz
cpu-icache	: 64KB
cpu-dcache	: 64KB
cpu-l2cache	: 1MB
cpu-tlb		: 1024 4-ways
cpu-cacheline	: 64Bytes
cpu-vector	: 0.7.1

processor	: 2
hart		: 2
isa		: rv64imafdcvsu
mmu		: sv39
cpu-freq	: 1.848Ghz
cpu-icache	: 64KB
cpu-dcache	: 64KB
cpu-l2cache	: 1MB
cpu-tlb		: 1024 4-ways
cpu-cacheline	: 64Bytes
cpu-vector	: 0.7.1

processor	: 3
hart		: 3
isa		: rv64imafdcvsu
mmu		: sv39
cpu-freq	: 1.848Ghz
cpu-icache	: 64KB
cpu-dcache	: 64KB
cpu-l2cache	: 1MB
cpu-tlb		: 1024 4-ways
cpu-cacheline	: 64Bytes
cpu-vector	: 0.7.1

[Dr-Noob]

I'm afraid the microarchitecture cannot be detected because cpuinfo is missing the uarch field. Regarding the SoC, we might be slightly more lucky. Can you show the output of cat /proc/device-tree/compatible?

PS: Is this a VM?

[bbonev]

cat /proc/device-tree/compatible
thead,light-valthead,light-lpi4athead,light

Note: there is no new line on the end.

No, it is not a VM, but still running the vendor modified Debian with kernel 5.10.113-lpi4a #2023.10.24.02.18+3e042d29a

[Dr-Noob]

I've added some patches to give support for your board. Now it should work everything except for the microarchitecture.

PS: Let me know if you have additional suggestions for the RISC-V backend 👍