drichmond Goto Github PK

aws-fpga

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

challenge-ii

PYNQ Hackathon 2017 Challenge 2

dramsim3

DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator

hops

Synthesizable Higher-Order Functions (Patterns) for C++

orca

RISC-V by VectorBlox

piccolo

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

pynq

Python Productivity for ZYNQ

pynq-copter

pynq-hackathon-2017

General Repository for PYNQ Hackathon Resources

pynq-hls

A Tutorial on Putting High-Level Synthesis cores in PYNQ

pynq-networking

Networking Overlay on PYNQ

pynq-zerotier-instructions

A short tutorial on how to install ZeroTier on PYNQ (2.3+)

pytest_utils

Package for producing Gradescope-compatible results.json files with Pytest tests

python-arduino-command-api

A Python library for communicating with Arduino microcontroller boards

readthedocs.org

source code to readthedocs.org

riffa-development

The RIFFA development repository

risc-v-on-pynq

RISC-V Integration for PYNQ

riscv-tests

rocket-chip

Rocket Chip Generator

rv12

RISC-V CPU Core

sampa-public

the Sampa group website

shef

Shielded Enclaves for Cloud FPGAs

verilator

Verilator open-source SystemVerilog simulator and lint system

vexriscv

A FPGA friendly 32 bit RISC-V CPU implementation

wireshark

Read-only mirror of Wireshark's Git repository. GitHub won't let us disable pull requests. ☞ THEY WILL BE IGNORED HERE ☜ Please upload them at https://code.wireshark.org/review/ .