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Joshua's Github


About Me



Some Projects


Researches

  • [Capstone Project] Harmonizing Grid Frequency: Investigating the Optimal Mix of Grid-Forming and Grid-Following Inverters in High Penetration Grids
  • [Communication Networks] Asynchronous VPPM VLC Algorithm

Recent Personal Projects

  • FPGA BASED Systolic Arrays (Planned for 2023-Winter)
    • Output Stationary, Weight Stationary Implementations
    • Scalable Systolic Array
    • Implemented in PL, interfaced by PS

Boards

  • Raspberry Pi 4B
  • Arduino Uno
  • Arduino Nano
  • ESP32
  • Raspberry Pico
  • Xilinx PYNQ-Z2 FPGA Development Board
  • [NEW] Tang Nano 9k RISCV FPGA Development Board

Software

  • Xilinx Vivado, Xilinx Vitis
  • GPGPU-Sim
  • Accel-Sim
  • Chipyard
  • LTSpice, PSPice, HSpice
  • Logism
  • MATLAB
  • PowerWorld
  • PSCAD

Joshua's Projects

chipyard icon chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

coding icon coding

Multicore Processor and GPU Programming <scratch code>

fpga-systolicarray icon fpga-systolicarray

Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis

hwacha icon hwacha

Microarchitecture implementation of the decoupled vector-fetch accelerator

kmap-solver icon kmap-solver

This simple kmap solver can solve 3 and 4 variable kmaps which is written in Python and interfaced using a .ipynb file. This was my final project in my Digital Logic Circuits course.

xv6-riscv-projects icon xv6-riscv-projects

xv6-riscv undergrad projects for EEE3535 Operating Systems (2022-Fall Semester) @ Yonsei University

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