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8-bits-risc-cpu-verilog

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（**处理器）简单结构和Verilog实现。

ahb-sramc

IC Verification & SV Demo

algo-practice

算法实践(JavaScript & Java)，排序，查找、树、两指针、动态规划等

algorithm

暴力、递归与分治、动态规划、贪心算法、回溯经典习题

algorithm-jiuzhang-basic-03-dynamic-programming

九章算法基础班 - 动态规划

booth_multiplier_radix_4

Verilog program

ccf

CGRA Compilation Framework

cnn_open

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

convolutional-neural-network

Implementation of CNN using Verilog

coremark

CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).

duan1213.github.io

floating-point-adder

32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog

floatingpoint_ieee754

Project about calculate the floating point number 32bit

fpga-proj

FPGA project

hello-world

just another repository

ieee754-format-32-bit-floating-point-adder

ieee754-single-precision-adder

ieee754-single-precision-multiplier

leetcode-master

LeetCode 刷题攻略：200道经典题目刷题顺序，共60w字的详细图解，视频难点剖析，50余张思维导图，支持C++，Java，Python，Go，JavaScript等多语言版本，从此算法学习不再迷茫！🔥🔥 来看看，你会发现相见恨晚！🚀

mnist_hls

Lenet for MNIST handwritten digit recognition using Vivado hls tool

multiplier16x16

Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder

radix-4_booth_multiplier

risc-v-cpu

RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.

risc-v-cpu-1

简易 risc-v 处理器设计

riscv

RISC-V CPU Core (RV32IM)

theoretical-basis

Basic knowledge of computer