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asic-design-roadmap

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.

astsee

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

carfield

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

chipsuite

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

cocotb-ahb

cocotbext-i3c

cxxrtl_eval

Experiments with Yosys cxxrtl backend

edalize

An abstraction library for interfacing EDA tools

esp

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

galois

gds-cell-library-render

gds2gcode

gds2gltf

gds3d

GDS3D is an application that can interpret so called IC layouts and render them in 3D.

gdsiistl

Converts GDSII files to STL files.

gdsiiview

Displays GDSII files as 3D geometry.

hal

HAL – The Hardware Analyzer

ipbb

IPbus Builder Tool

logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

logisim

Logisim Italian Fork

magic

Magic VLSI Layout Tool

mflowgen

mflowgen -- A Modular ASIC/FPGA Flow Generator

network-on-chip-router

Synthesize and P&R an Network-on-Chip Router

networkonchip

Development of a Network on Chip Simulation using SystemC.

noc-py

Python modules/classes for easy analysis of Network on Chips

noxim

Network on Chip Simulator

opendb

Database and Tool Framework for EDA

openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.