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Bhavya Vasudeva's Projects

32-bit-alu icon 32-bit-alu

A 32-bit ALU with carry look ahead adder and ripple carry adder and provision for signed and unsigned numbers.

cmid icon cmid

Code for the Conditional Mutual Information-Debiasing (CMID) method.

co-vegan icon co-vegan

Co-VeGAN: Complex-Valued Generative Adversarial Network for Compressive Sensing MR Image Reconstruction

led-matrix icon led-matrix

A project with arduino and shift registers which displays letters(moving and static) in the form of an 8x5 LED matrix.

lime icon lime

Implementation of the paper, "LIME: Low-Light Image Enhancement via Illumination Map Estimation"

risc icon risc

Verilog implementation of the 32-bit RISC processor.

starter-academic icon starter-academic

🎓 Easily create a beautiful academic résumé or educational website using Hugo, GitHub, and Netlify

verilog-assignments icon verilog-assignments

This repository contains some Verilog files in which DLD concepts like adders, multiplexer, multiplier, flip-flops, encoder etc. have been implemented.

wilds icon wilds

A machine learning benchmark of in-the-wild distribution shifts, with data loaders, evaluators, and default models.

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