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3-stage-pipeline

A Three Stage Pipeline 16-bit processor implemented in Verilog

binutils-gdb

clone of git://sourceware.org/git/binutils-gdb.git

boom-template

A template for building new projects/platforms using the BOOM core.

cmpe220fall16

Public repository of the UCSC CMPE220 class project

desesc

Dromajo ESESC

dolma

ferdous313

invisispec-1.0

Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.

lima

mips

Verilog behavioral modeling of a 5-stage pipeline MIPS processor with builtin L1 cache.

nilufar_ferdous_resume

open

openram

openram_2017

OpenRAM: an open-source memory compiler for VLSI circuits.

openram_sram

openram_sram_2018

openram_sram_cell

openram_sram_multiported

openram_sram_multiported_

or1200

OpenRISC 1200 implementation

riscv

rocket-chip

Rocket Chip Generator

rrip

RRIP simulation

rv12

RISC-V CPU Core

sdo

simulator_cpu

Pipeline CPU of MIPS architecture with L1 Data Cache by Verilog

sram-_multiported_openram

sram_multiported_cell

vim-pyrope_trial

vim_pyrope_working