Related Issues (20)
- (Chrome) Web circuit viewer not zoomed to fit iframe size HOT 1
- Export to Verilog
- (Edge) Web circuit viewer is empty, no content at all
- Transistors represented as open switches during simulation HOT 2
- Non-volatile RAM (NVRAM)
- Memory contents as project objects
- RAM and ROM as symbol controls
- Width of "Hierarchy" sidebar cannot be reduced
- DSL scripts produce unexpected error when comparing undefined values
- False positive test results with undefined signals
- False positive test result with ports of type "inout"
- Error while creating junction from small wire
- Pan animation towards copy/pasted components
- Errors occurring during "Save" can lead to corrupt files
- Components draw propDelay expression instead of value during single-step simulation
- Wire tooltip "Press ALT to create junction" displayed on read-only circuits
- Capacitor component (analog)
- Monostable multivibrator (Monoflop) using capacitor
- New DSL scripting function "triggerAfter()"
- Error in DSL exec script when using integer numbers in analog circuit
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