Mnemonics of XNOR gate are off

[richardabendroth]

Mnemonics of XNOR gate are off

[flandreas]

By "off" I guess you mean that the lower input of the XNOR is internally guided to the top of the gate.

Well, this is done intentionally. Let me explain.

1. The internal "double bar" switches are generally meant to be in rest with input 0, and pushed against an imaginary spring with input 1.
2. XNOR produces output 1 if and only if both inputs are the same.
3. Both internal "double bar" switches are at the same vertical position when at rest.
4. To achieve the XNOR behaviour, both "double bar" switches must move into the same direction when being pushed by a 1 input.
5. Therefore, the lower external gate input must be guided to the top of the gate in order to push down for input 1.

I understand that the internal wiring might look confusing, but the main take-away is that the "double bar" switches must be at the same height (y position) to produce the XNOR logic.

I didn't see a way how this can be achieved with simpler internal wiring. Do you have an idea?

[richardabendroth]

I see, you are using a relay analogy. I was more thinking of a combination of serial/parallel arrangement of transistors where input and output negations basically just change the type of transistor (n/p): on when powered or off when powered. To be very honest, for me, it's harder to wrap my head around the relay analogy. It implies somehow a negation in one's head when thinking about it. The question is if the mnemonics should explain how an equivalent relay arrangement would work or what arrangement of transistors builds up the respective gate.

[flandreas]

@richardabendroth I had more of a mechanical model in mind, but you're right, since relays are electro-magnecti-mechanical components, relay is probably the correct term.

The purpose of the mnemonics is to provide one of many possible answers to the question "But how does a logic gate word?". I've developed them before I've had the transistors, so I had to come up with something else. Would the transistor model be easier to understand? I don't think so. I barely have an intuitive understanding of how a single transistor works, let alone how a couple of them work together to build a function like NAND or XNOR. Instead, when I look at the mnemonics and observe how current flows through the inner switches, I instantly understand that both inputs of an XNOR must have the same value to make the output 1.

But I understand that this might be different for different people. Maybe in the long run, mnemonic will disappear again and will be replaced by different internal implementations the user can open for inspection, i.e. Antares' upcoming "Analog" layer containing real analog transistors, or a mechanical layer, or a layer with a water flow model, a pure mechanical model, or whatever the user might prefer.

The analog layer itself could be backed up by an even more fundamental semi-conductor layer where the user would see electric fields, electrons, and holes moving around. But implementing that I'll delay until my retirement time.. ;-)