Related Issues (20)
- Bit extender has undefined output at simulation start
- Foreground/border of color "Blue" could be darker with dark mode themes
- "inconsistent net value" between tri-state buffer output and input/output pin HOT 8
- Default value for pins HOT 3
- "Subsystem" rectangles missing in SVG output
- Unexpected error if workspace directory doesn't exist any more
- Inconsistent circuit state after failed copy/paste
- Simulation doesn't launch when initializing subcircuit inputs with DSL script HOT 1
- Bit accessor DSL operator doesn't work on pins HOT 7
- (Chrome) Web circuit viewer not zoomed to fit iframe size HOT 1
- Export to Verilog
- (Edge) Web circuit viewer is empty, no content at all
- Transistors represented as open switches during simulation HOT 2
- Non-volatile RAM (NVRAM)
- Memory contents as project objects
- RAM and ROM as symbol controls
- Width of "Hierarchy" sidebar cannot be reduced
- DSL scripts produce unexpected error when comparing undefined values
- False positive test results with undefined signals
- False positive test result with ports of type "inout"
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