Comments (6)
Reproducible when deleting the selected wire in this simplified circuit:
The problem occurs when the wire that gets joined is connected with yet another junction node.
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Thanks for taking care of this! I tested it on the head of master and now this one reproduces a malfunction:
antares.mp4
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Thanks! Reopened
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Cannot be reproduced generally with a simple circuit having the same structure like the problematic region like in the video.
However, it CAN be reproduced using the dump provided in #713 with exactly the wire segment you've deleted. I'll investigate..
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Great find, I think all instances in which I've encountered this bug previously were related to long wire junction ladders like this.
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Unfortunately I think I've introduced this one with my last fix. The scenario above isn't reproducible in the productive version 1.11.1.
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Related Issues (20)
- Circuit image thumbnail in Antares Web
- Wrong labels for D Flip-Flops HOT 1
- bit-extender with 1 bit output HOT 6
- Export circuit as raster image (gif, png, jpg)
- Bit extender has undefined output at simulation start
- Foreground/border of color "Blue" could be darker with dark mode themes
- "inconsistent net value" between tri-state buffer output and input/output pin HOT 8
- Default value for pins HOT 3
- "Subsystem" rectangles missing in SVG output
- Unexpected error if workspace directory doesn't exist any more
- Inconsistent circuit state after failed copy/paste
- Simulation doesn't launch when initializing subcircuit inputs with DSL script HOT 1
- Bit accessor DSL operator doesn't work on pins HOT 7
- (Chrome) Web circuit viewer not zoomed to fit iframe size HOT 1
- Export to Verilog
- (Edge) Web circuit viewer is empty, no content at all
- Transistors represented as open switches during simulation HOT 2
- Non-volatile RAM (NVRAM)
- Memory contents as project objects
- RAM and ROM as symbol controls
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