z80: fetch opcode timing

[WilfriedRabouin]

z80: fetch opcode timing

[floooh]

Arguably yes, in the tracelog (from https://floooh.github.io/visualz80remix/) the instruction register (OP) is loaded between M1/T2 and M1/T3, but the data bus value already flips in M1/T2 (because the emulated memory system doesn't have any latency).

┌─────────┬────┬──────┬──────┬──────┬────┬────┬──────┬────┬──────┬────┬──────────────┐
│ Cycle/h │ M1 │ MREQ │ IORQ │ RFSH │ RD │ WR │ AB   │ DB │ PC   │ OP │ Asm          │
├─────────┼────┼──────┼──────┼──────┼────┼────┼──────┼────┼──────┼────┼──────────────┤
│     1/0 │ M1 │      │      │      │    │    │ 0000 │ 00 │ 0000 │ 00 │ LD SP,0030h  │
│     1/1 │ M1 │ MREQ │      │      │ RD │    │ 0000 │ 00 │ 0001 │ 00 │ LD SP,0030h  │
│     2/0 │ M1 │ MREQ │      │      │ RD │    │ 0000 │ 31 │ 0001 │ 00 │ LD SP,0030h  │
│     2/1 │ M1 │ MREQ │      │      │ RD │    │ 0000 │ 31 │ 0001 │ 00 │ LD SP,0030h  │
│     3/0 │    │      │      │ RFSH │    │    │ 0000 │ 31 │ 0001 │ 31 │ LD SP,0030h  │
│     3/1 │    │ MREQ │      │ RFSH │    │    │ 0000 │ 31 │ 0001 │ 31 │ LD SP,0030h  │
│     4/0 │    │ MREQ │      │ RFSH │    │    │ 0000 │ 31 │ 0001 │ 31 │ LD SP,0030h  │
│     4/1 │    │      │      │ RFSH │    │    │ 0000 │ 31 │ 0001 │ 31 │ LD SP,0030h  │

I'm loading the value in M1/T2 because that's the following clock cycle after the memory read was intiated, but moving it one clock cycle later wouldn't break anything (e.g. the Z80 emulation expects that the tick function doesn't modify the data bus pins if no requests must be handled, but it also expects that the data bus has been updated in the next clock cycle for read requests).

But as I wrote in the blog post here, I took some liberties to allow a simpler and more performant system tick function.

For a proper "Ben Eater syle breadboard emulator" it would be better if the pin timings would behave exactly as a real Z80.