Comments (7)
What is LSU?
from 16bitjs.
in a 32-bit RISC CPU for instance, there are 4 main components:
- ALU: Arithmetic/Logical Unit (32 ยค 32 -> 32 with no latency)
- MDU: Multiply/Divide Unit (32 * 32 -> 64, 64 + 32 * 32 -> 64, 32 ยค 32 -> 32 with long latency)
- LSU: Load/Store Unit
- BCU: Branch Control Unit
from 16bitjs.
OK this is why I think the discussion phase of a proposal is quite important. It's nice to be on the same page about a potential implementation. I'm assuming here then that you want to add a module (lsu.js) to the cpu. In that module you'll handle all load/store based instructions directly. Is that correct?
from 16bitjs.
I was coining the term LSU from hardware viewpoint, not from software viewpoint. So there is no such lsu.js. But I found weird to make the offset adoption for LDR and STR separately as features because in hardware the computation of an effective address is done by the same hardware instance. I saw you finally integrate one of my three implementations. I was in the process to make them in one PR to keep coherency .
from 16bitjs.
I see where the miscommunication took place. This is a software project, and I really do believe it's important to implement every piece individually. Each instruction can be rewritten in isolation, and so it should be . You can imagine the situation where we split those 3 issues between us and I wrote one and you wrote one. That's only possible when you isolate features. It's also a lot easier to review code when it only touches a single concept. I understand your reasoning, but I believe this is how features should be implemented.
from 16bitjs.
Anyway, things in my repository went awry so I've just added the two remaining PRs as such. I need to fix the mess in my repository when all those PRs are done.
from 16bitjs.
Hey I resolved all the merge conflicts and merged the pull requests so all of these steps are in place. It was quite a bit of work because like you say - the repos got pretty haywire. For future enhancements let's chat about the least conflicting workflow first to avoid the same again, but overall awesome! Thanks ๐
from 16bitjs.
Related Issues (20)
- LDV16 B, value probably doesn't work HOT 1
- LICENCE isn't filled in HOT 2
- Replace JMP with a CMP instruction, and rename JMR to JMP HOT 11
- Extend LDR with offset mode HOT 4
- LDV - a better way to deal with 16-bit immediate value HOT 7
- Security issue: code execution when assembling files HOT 2
- Merge SYS, HLT and RET since they no arguments HOT 4
- Trouble to use "node src/assembler" HOT 2
- MOV - using the upper 8 bits to store a sign-extended immediate as an addend HOT 2
- Add optional offset to LDR HOT 1
- Rename LDM to STA HOT 1
- Rename LDP to STR with an optional 8 bit offset HOT 6
- Refactor JLT to JCP (Jump ComPare) HOT 1
- An example (but incomplete) of ISA using almost the same rules of 16bitjs
- Improve debugger HOT 6
- Convert to signed 16 but integer format HOT 1
- SWAP - this pseudo can be done through 3 XORs HOT 10
- STACK - some RISC CPUs don't have a PUSH and POP instructions
- Missing ESLint configuration HOT 2
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from 16bitjs.