Comments (3)
paulb-nl
commented on May 12, 2024
1
REJO and PYNU are Set-Reset latches according to GateBoy and that makes sense.
REJO is set by SARY and reset by (INT_VLB | RESET_VIDEO2)
PYNU is set by NUNU and reset by XOFO.
from dmg-cpu-inside.
paulb-nl
commented on May 12, 2024
1
Great! Thanks for letting me know about your schematics.
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msinger
commented on May 12, 2024
Hi, it seems like for some reason @furrtek doesn't look into this project anymore. I'm a little bit afraid I opened too many issues. 😟
@rgalland and I, we have made a KiCad schematic here: https://github.com/msinger/dmg-schematics
We (hopefully) fixed everything. If you find any mistakes, we would be happy to hear from you.
SARY (Window Y Match) latch is clocked by TALU (1Mhz).
This and what you wrote in your second comment is correct.
Those NAND and NOR latches are in quite some other places. See issue #29.
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Related Issues (20)
- Adders EFYK and EJOK got wrong input
- Clock inputs of FF25 register need to be inverted one more time HOT 2
- GAXU is an AND, not a NAND
- XECY is wrong flip-flop type
- Wrong input 4 for CUGU
- BUDA needs inverted CPU_RD
- Reset of registers FF24 and FF25 is wrong
- KYNY and KYLY are two names for the same cell
- KAKE in an OR gate
- DOXA is a NOR gate
- BYHO has wrong input
- HAFE is a NOR gate
- Rare type of single-output flip-flop may have Q instead of !Q
- APU CH1 and CH2 volume envelope only work when AOI_MUX_2 cells have output inverted HOT 2
- HYNO is AND
- Misleading notes/labels on page 20 (APU CH4)
- ETAN is a NOR
- GOJY is connected to wrong output of EMER
- HUDA is an AND
- KOTA and JAFA are AND gates
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