Comments (7)
I wonder if we should be looking up dr7 with PEEKUSR - see for example
http://lxr.free-electrons.com/source/tools/testing/selftests/breakpoints/breakpoint_test.c#L84
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Hmm.. we likely should be reading the original value in order to preserve the control bits set for other regs aside from the one we are currently setting - however I'm not sure if this is what is causing the failure above.
Along with this is a bug of the current implementation - it currently is setting dr7 bits for the base register DR0, and is not setting the values correctly for DR1-3.
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If you're happy to wait a bit I can try come up with a fix over weekend/Monday, else happy to test proposed fixes
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Check out http://en.wikipedia.org/wiki/X86_debug_register#DR7_-_Debug_control for more info on what I described above, also you may want to have a look at the intel manual: http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-system-programming-manual-325384.pdf specifically chapter 17.
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@pnasrat yeah definitely, that's no problem.
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Maybe an alignment issue? The hw breakpoints are set with DR_LEN_8 which I
seem to remember requires the address to be 8-byte aligned.
Here's my attempt to fix this, enable dr1-dr3 usage and to generally be more
careful with the control bits ebfe/delve@c0b84352f1
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I can confirm that at ebfe/delve@c0b8435 when I run
go test -v .
On the box in question it all passes - I suggest you amend the commit message to add a fixes
line in the commit for this issue as per
https://help.github.com/articles/closing-issues-via-commit-messages/
before sending the pull request. Thanks, sorry not to have had time this evening to look at.
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