Use of L2 in FPGA setups

[bala122]

Use of L2 in FPGA setups

[tcal-x]

Hi @bala122 , this question is more about the LiteX SoC architecture, so it might be worth asking on the #litex IRC channel (or find them on discord as well these days).

But I can take a guess --- even with the same building blocks, the BRAMs can be organized differently. I expect that the L2 cache can transfer wide data lines to/from the SDRAM with multiple BRAMs in parallel, and then connect to the 32b Wishbone bus. The Wishbone system bus is between the L2 cache and the VexRiscv's L1 caches. The L1 caches are tightly integrated with the VexRiscv's pipeline. So they each serve specific purposes; eliminating either the L1 or L2 cache and putting all of its resources to the other side would likely hurt performance.