Comments (1)
Apart from harvard-acc/ALADDIN#43, the other question is why this only happens with MemoryPolicy = AllCache, rather than DMA or ACP. The reason here is that in gem5-aladdin, when we say "map this array to a cache", we really mean "replace the scratchpad for this array with an L1 cache entirely". It applies only to the memory on the accelerator side. But in the SMAUG context, the memory policy of "AllCache" just means "when you copy data from the host to the accelerator, get the data from the host through normal virtual memory, not by sending DMA or ACP requests". In other words, "caching" in a MemoryPolicy refers to the mechanism of how you get the data, not the physical place where data is stored.
This mode of fetching data is not supported in gem5-aladdin because it's really no different from using ACP as the transport mechanism. I will send a patch to remove AllCache as a valid MemoryPolicy, because it's not.
If you were interested in replacing the scratchpads on the accelerators with a cache, that's done differently. Go into the smv-accel.cfg file (which configures the accelerator) and replace all the "partition,cyclic" lines with "cache". Then configure the cache itself in gem5.cfg by changing memory_type=cache
and updating cache_size=xxkB
. This will require #104 to fix a small bug with missing files. Once that's submitted, update SMAUG's submodules (git submodule update), and it should work for you (I just tested it).
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Related Issues (20)
- Catch2 unit tests OOM when using the JUnit reporter
- Simplify Python module naming for easier usage
- Clean up files from SMAUGv1
- Clean up public APIs that may not need to be public or exist at all
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- Workspace::addTensor may leak memory if a Tensor name is reused
- Update Dockerfile and image with doc generator prereqs HOT 1
- Improve documentation for SMV backend
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- Question about DMA setup time modeling HOT 2
- Systolic array loops when feature size is the same of kernel size HOT 1
- Can we run multiple instances of NVDLA minerva model on smaug . HOT 2
- Fail to replace accelerator spad with cache: `RuntimeError: Unknown array "inputs".` HOT 2
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- Can I simulate the accelerator whose clock frequency is larger than 1GHz HOT 3
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