.github

Default files for all repositories in the iDoka's account on GitHub

asciidoc-table-beautifier

This repository contains a script that visually formats simple tables in asciidoc files into a more readable format.

asic-pinout-drawer

Simple pin assignment generator for IC case

awesome-automotive-can-id

:tractor: Collect of CAN IDs and its payloads for various car brands/models in one place. Might be useful for Cyber Security Researchers, Reverse Engineers, and Automotive Electronics Enthusiasts.

awesome-canbus

:articulated_lorry: Awesome CAN bus tools, hardware and resources for Cyber Security Researchers, Reverse Engineers, and Automotive Electronics Enthusiasts.

awesome-embedded-software

:stars: List of software (HW interfaces, libs, protocols, etc) specifically suitable for resource-constrained Embedded Systems (low-memory and low-power) like 8-bit, 16-bit and 32-bit microcontrollers.

awesome-fpga-boards

:atm: Second life for FPGA boards which can be repurposed to DYI/Hobby projects ...............................................................................................

awesome-linbus

:articulated_lorry: An awesome LIN bus tools, hardware and resources. It helps a reverse engineering LIN bus devices with lightly specializing in automotive embedded controller software and communication understanding.

awesome-nrf5

nRF5xxxx family

awesome-nrf5x

nRF51|nRF52 useful resources

awesome-stm8

STM8 awesome list

corsair

Control and Status Register map generator for HDL projects

dell-latitude-e7470

Linux and Dell Latitude E7470 story and fixed issues

digikey-cool-stuff

Collection of scripts related to DigiKey

dotfiles

.files from my homebrewed CentOS 7 | Ubuntu 18.04

eda-scripts

Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)

gitstats

git history statistics generator

gnss-verilog-signal-simulator

GNSS Signal Generator writen on Verilog HDL for SDR platform (currently BladeRF)

gost-28147-89

Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher

gost-r34.12-2015

Verilog HDL implementation of the GOST R34.12-2015 — a fresh Russian government standard symmetric key block cipher.

hdl-coding-style-standards

Collection of Coding Style Standards for Verilog and VHDL

hdl-secded-producer

MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.

hdl-stuff

HDL things for FPGA and ASIC

hdlparse

Simple Python parser for extracting HDL (VHDL or Verilog) documentation

idoka

Config files for my GitHub profile

idoka.github.io

iDoka's web page on Github

ipxact-cli-tools

IP-XACT based CLI-tools

ipyxact

Python-based IP-XACT parser

mastering-fpgasic-book

:book: Mastering FPGASIC Book

mch2022-badge-hardware