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I am a Ph.D. Candidate in FPGA/Parallel Computing Lab at University of Southern California, advised by Prof. Prasanna. I'm interested in Graph Neural Networks, Hardware Accelerators/HPC, and Heterogeneous Computing. I have published several papers in HPC-, ASIC-, and FPGA-related conferences in the past three years. Please refer to my personal website for more details.

In addition to research interests, I'm also interested in video editing and photography. Check out my vlogs and photos.

I completed my undergraduate study in National Taiwan University (NTU), majored in Electrical Engineering. I was also an Electrical Engineering Intern at Hewlett-Packard (HP), Taipei.

Yi-Chien Lin's Projects

a-single-path-delay-32-point-fft-processor icon a-single-path-delay-32-point-fft-processor

A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.

argo icon argo

Official implementation of ARGO, an auto-tuning runtime system for GNN training on CPU.

dgl icon dgl

Python package built to ease deep learning on graph, on top of existing DL frameworks.

gcn icon gcn

Implementation of Graph Convolutional Networks in TensorFlow

hp-gnn icon hp-gnn

Generating High Throughput GNN Training Implementation on CPU-FPGA Heterogeneous Platform

jasonlin316.github.io icon jasonlin316.github.io

Github Pages template for academic personal websites, forked from mmistakes/minimal-mistakes

minimal-mistakes icon minimal-mistakes

:triangular_ruler: Jekyll theme for building a personal site, blog, project documentation, or portfolio.

risc-v-cpu icon risc-v-cpu

A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.

systolic-array-for-smith-waterman icon systolic-array-for-smith-waterman

This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times faster than a software running the same algorithm.

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