__sync_lock_release generates incorrect code

[jbush001]

__sync_lock_release generates incorrect code

[jbush001]

The LLVM IR is:

  store atomic i32 0, i32* %lk release, align 4
  ret i32 undef

[jbush001]

Because the action for ISD::ATOMIC_STORE is expand, it gets turned into an AtomicSwap:

Legalizing: t4: ch = AtomicStore<Volatile ST4[%lk]> t0, t2, Constant:i32<0>
Trying to expand node
Succesfully expanded node
 ... replacing: t4: ch = AtomicStore<Volatile ST4[%lk]> t0, t2, Constant:i32<0>
     with:      t9: i32,ch = AtomicSwap<Volatile ST4[%lk]> t0, t2, Constant:i32<0>

This has a custom emitter, which calls the common EmitAtomicBinary.

  case Nyuzi::ATOMIC_SWAP:
    return EmitAtomicBinary(MI, BB, 0);

When the third parameter is zero, this doesn't emit the swap, but erroneously just copies the old value:

  if (Opcode != 0) {
    ....
  } else
    NewValue = OldValue; // This is just swap: use old value

[jbush001]

Can reproduce issue by fixing test:

--- a/test/CodeGen/Nyuzi/atomics.ll
+++ b/test/CodeGen/Nyuzi/atomics.ll
@@ -127,8 +127,9 @@ define i32 @atomic_xchg(i32* %ptr, i32 %value) { ; CHECK-LABEL: atomic_xchg:
 
   ; CHECK: load_sync [[OLDVAL:s[0-9]+]], (s0)
   ; CHECK: move s{{[0-9]+}}, [[OLDVAL]]
-  ; CHECK: store_sync [[OLDVAL]], (s0)
-  ; CHECK: bz [[OLDVAL]],
+  ; CHECK: move [[NEWVAL:s[0-9]+]], s1
+  ; CHECK: store_sync [[NEWVAL]], (s0)
+  ; CHECK: bz [[NEWVAL]],
 
   ret i32 %tmp
 }

[jbush001]

Also, using load/store sync is overkill for this. An store/membar would do the job more efficiently.

[jbush001]

I didn't do the work to make this just be a store. I'll file another bug for that.