RK3568 and kernel 5.10

[jeffycn]

RK3568 and kernel 5.10

[JeffyCN]

normally nothing else, the internal bsp 5.10 kernel already support 356x, but i've been warned not to provide newer version for 5.10 here(due to company policy).

so maybe try to contact rockchip FAE for newest kernel...

[Shaggy013]

All that kernel naming ;) , and so many flavors now 4.19, 5.10 and mainline (without npu) .

Nanopi has already a vendor rockchip 5.10 kernel for their rk356x boards ;) only indeed not a yocto in their sdfuse-rk3568 , ah well here is a start ;)

meta-local/recipes-kernel/linux/linux-rockchip_5.10.bbappend

SRC_URI = "
git://github.com/friendlyarm/kernel-rockchip.git;protocol=https;nobranch=1;branch=nanopi5-v5.10.y_opt;
"
SRCREV = "${AUTOREV}"

and conf/machine/include/rk356x.inc

PREFERRED_VERSION_linux-rockchip ?= "5.10%"
LINUXLIBCVERSION ?= "5.10-custom%"

and when building in SDk rename kernel folder so it wont use local for building kernel

and watch wich mali version is needed for kernel

ow and choose the right dts .

rk3568-nanopi5-rev01.dts is for r5s
rk3568-nanopi5-rev02.dts and rk3568-nanopi5-rev03.dts is for r5c

and if uboot keeps giving trouble you can replace it with the vendor rockchip uboot

https://github.com/friendlyarm/uboot-rockchip.git
SRCREV= "8c91d15ff7d106d0da37c23727b387c2d6883e8b"

ow and uboot defconfig then nanopi5_defconfig

[JeffyCN]

check:
https://github.com/JeffyCN/yocto-conf
https://github.com/JeffyCN/yocto-manifests

[tmm1]

I was able to build working kernel with this layer:

$ cat meta-local/recipes-kernel/linux/linux-rockchip_5.10.bbappend
SRC_URI = " \
    git://github.com/rockchip-linux/kernel.git;protocol=https;nobranch=1;branch=develop-5.10; \
"
SRCREV = "${AUTOREV}"

[chrisiberg]

It does not work for me, I don't get a boot logo at all, just black.
Is it possible, that only the 4.19 .wic is booting from SD-Card?
@tmm1 did you use your own fork and was the "linux-rockchip_5.10.bbappend" the only mod?

the serial log:

DDR Version V1.13 20220218<CR><LF>
In<CR><LF>
ddrconfig:0<CR><LF>
LPDDR4X, 324MHz<CR><LF>
BW=32 Col=10 Bk=8 CS0 Row=17 CS=1 Die BW=16 Size=4096MB<CR><LF>
tdqss: cs0 dqs0: 48ps, dqs1: -72ps, dqs2: 48ps, dqs3: -24ps, <CR><LF>
<CR><LF>
change to: 324MHz<CR><LF>
PHY drv:clk:36,ca:36,DQ:29,odt:0<CR><LF>
vrefinner:24%, vrefout:41%<CR><LF>
dram drv:40,odt:0<CR><LF>
clk skew:0x60<CR><LF>
<CR><LF>
change to: 528MHz<CR><LF>
PHY drv:clk:36,ca:36,DQ:29,odt:0<CR><LF>
vrefinner:24%, vrefout:41%<CR><LF>
dram drv:40,odt:0<CR><LF>
clk skew:0x58<CR><LF>
<CR><LF>
change to: 780MHz<CR><LF>
PHY drv:clk:36,ca:36,DQ:29,odt:0<CR><LF>
vrefinner:24%, vrefout:41%<CR><LF>
dram drv:40,odt:0<CR><LF>
clk skew:0x58<CR><LF>
<CR><LF>
change to: 1560MHz(final freq)<CR><LF>
PHY drv:clk:36,ca:36,DQ:29,odt:60<CR><LF>
vrefinner:16%, vrefout:22%<CR><LF>
dram drv:40,odt:80<CR><LF>
vref_ca:00000071<CR><LF>
clk skew:0x13<CR><LF>
cs 0:<CR><LF>
the read training result:<CR><LF>
DQS0:0x34, DQS1:0x35, DQS2:0x32, DQS3:0x37, <CR><LF>
min  : 0xd  0xd  0xf  0xf  0x1  0x5  0xa  0x5 , 0x7  0x1  0xb  0xf  0xf 0x12 0x16  0xf ,<CR><LF>
       0xe  0xb  0x6  0x6  0x1  0x2  0x2  0x5 , 0xb  0xa  0x5  0x2  0xf  0xf 0x12  0xe ,<CR><LF>
mid  :0x28 0x29 0x2a 0x2a 0x1c 0x1f 0x25 0x21 ,0x20 0x1c 0x25 0x29 0x29 0x2c 0x2f 0x29 ,<CR><LF>
      0x28 0x27 0x21 0x1f 0x1b 0x1c 0x1c 0x1f ,0x27 0x26 0x20 0x1e 0x2b 0x2c 0x2d 0x29 ,<CR><LF>
max  :0x44 0x46 0x45 0x45 0x38 0x39 0x41 0x3d ,0x3a 0x37 0x3f 0x44 0x44 0x46 0x49 0x44 ,<CR><LF>
      0x42 0x44 0x3c 0x39 0x36 0x37 0x37 0x3a ,0x44 0x42 0x3c 0x3a 0x47 0x49 0x48 0x44 ,<CR><LF>
range:0x37 0x39 0x36 0x36 0x37 0x34 0x37 0x38 ,0x33 0x36 0x34 0x35 0x35 0x34 0x33 0x35 ,<CR><LF>
      0x34 0x39 0x36 0x33 0x35 0x35 0x35 0x35 ,0x39 0x38 0x37 0x38 0x38 0x3a 0x36 0x36 ,<CR><LF>
the write training result:<CR><LF>
DQS0:0x1c, DQS1:0x5, DQS2:0x1c, DQS3:0xf, <CR><LF>
min  :0x67 0x6b 0x6a 0x6b 0x5c 0x5f 0x65 0x65 0x63 ,0x47 0x45 0x4d 0x53 0x51 0x54 0x55 0x54 0x4e ,<CR><LF>
      0x69 0x68 0x60 0x5f 0x5c 0x5c 0x5c 0x63 0x62 ,0x54 0x56 0x4f 0x4e 0x5b 0x5e 0x5b 0x5c 0x54 ,<CR><LF>
mid  :0x80 0x84 0x81 0x83 0x75 0x77 0x7d 0x7c 0x7a ,0x5f 0x5d 0x66 0x6a 0x6b 0x6d 0x6d 0x6a 0x67 ,<CR><LF>
      0x84 0x82 0x7a 0x79 0x76 0x76 0x76 0x7b 0x7b ,0x6e 0x6f 0x68 0x68 0x76 0x77 0x75 0x75 0x6d ,<CR><LF>
max  :0x99 0x9d 0x99 0x9b 0x8e 0x90 0x96 0x94 0x91 ,0x77 0x75 0x7f 0x82 0x85 0x86 0x86 0x81 0x80 ,<CR><LF>
      0x9f 0x9c 0x94 0x93 0x90 0x90 0x90 0x94 0x94 ,0x89 0x88 0x82 0x82 0x91 0x90 0x90 0x8e 0x86 ,<CR><LF>
range:0x32 0x32 0x2f 0x30 0x32 0x31 0x31 0x2f 0x2e ,0x30 0x30 0x32 0x2f 0x34 0x32 0x31 0x2d 0x32 ,<CR><LF>
      0x36 0x34 0x34 0x34 0x34 0x34 0x34 0x31 0x32 ,0x35 0x32 0x33 0x34 0x36 0x32 0x35 0x32 0x32 ,<CR><LF>
CA Training result:<CR><LF>
cs:0 min  :0x40 0x36 0x42 0x35 0x40 0x34 0x40 ,0x43 0x36 0x42 0x35 0x40 0x34 0x40 ,<CR><LF>
cs:0 mid  :0x7a 0x7a 0x7d 0x79 0x7a 0x78 0x6b ,0x7b 0x79 0x7a 0x78 0x78 0x78 0x6a ,<CR><LF>
cs:0 max  :0xb5 0xbe 0xb8 0xbd 0xb4 0xbd 0x97 ,0xb4 0xbd 0xb3 0xbc 0xb0 0xbd 0x94 ,<CR><LF>
cs:0 range:0x75 0x88 0x76 0x88 0x74 0x89 0x57 ,0x71 0x87 0x71 0x87 0x70 0x89 0x54 ,<CR><LF>
out<CR><LF>
U-Boot SPL board init<CR><LF>
U-Boot SPL 2017.09-gc2dee0fa582-220119 #root (Mar 04 2022 - 11:39:23)<CR><LF>
unknown raw ID phN<CR><LF>
unrecognized JEDEC id bytes: 00, 00, 00<CR><LF>
Trying to boot from MMC2<CR><LF>
No misc partition<CR><LF>
Trying fit image at 0x4000 sector<CR><LF>
## Verified-boot: 0<CR><LF>
## Checking atf-1 0x00040000 ... sha256(fe4f274c06...) + OK<CR><LF>
## Checking uboot 0x00a00000 ... sha256(d16f16c89f...) + OK<CR><LF>
## Checking fdt 0x00b32938 ... sha256(9679fe2a45...) + OK<CR><LF>
## Checking atf-2 0x00068000 ... sha256(8d44036095...) + OK<CR><LF>
## Checking atf-3 0xfdcd0000 ... sha256(e410275b51...) + OK<CR><LF>
## Checking atf-4 0xfdcc9000 ... sha256(990c53fc01...) + OK<CR><LF>
## Checking atf-5 0x00066000 ... sha256(315a4195a9...) + OK<CR><LF>
## Checking optee 0x08400000 ... sha256(f3f0302d4c...) + OK<CR><LF>
Jumping to U-Boot(0x00a00000) via ARM Trusted Firmware(0x00040000)<CR><LF>
Total: 472.659 ms<CR><LF>
<CR><LF>
INFO:    Preloader serial: 2<CR><LF>
<SOH>�NOTICE:  BL31: v2.3():v2.3-181-gc9a647cae:cl<CR><LF>
NOTICE:  BL31: Built : 10:55:41, Oct 18 2021<CR><LF>
INFO:    GICv3 without legacy support detected.<CR><LF>
INFO:    ARM GICv3 driver initialized in EL3<CR><LF>
INFO:    pmu v1 is valid<CR><LF>
INFO:    dfs DDR fsp_param[0].freq_mhz= 1560MHz<CR><LF>
INFO:    dfs DDR fsp_param[1].freq_mhz= 324MHz<CR><LF>
INFO:    dfs DDR fsp_param[2].freq_mhz= 528MHz<CR><LF>
INFO:    dfs DDR fsp_param[3].freq_mhz= 780MHz<CR><LF>
INFO:    Using opteed sec cpu_context!<CR><LF>
INFO:    boot cpu mask: 0<CR><LF>
INFO:    BL31: Initializing runtime services<CR><LF>
INFO:    BL31: Initializing BL32<CR><LF>
I/TC: <CR><LF>
I/TC: OP-TEE version: 3.13.0-619-g48b7c13e2 #hisping.lin (gcc version 10.2.1 20201103 (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16))) #7 Thu Jan  6 17:13:25 CST 2022 aarch64<CR><LF>
I/TC: Primary CPU initializing<CR><LF>
I/TC: Primary CPU switching to normal world boot<CR><LF>
INFO:    BL31: Preparing for EL3 exit to normal world<CR><LF>
INFO:    Entry point address = 0xa00000<CR><LF>
INFO:    SPSR = 0x3c9<CR><LF>
<CR><LF>
<CR><LF>
U-Boot 2017.09 (Jan 10 2022 - 01:38:43 +0000)<CR><LF>
<CR><LF>
Model: Rockchip RK3568 Evaluation Board<CR><LF>
PreSerial: 2, raw, 0xfe660000<CR><LF>
DRAM:  4 GiB<CR><LF>
Sysmem: init<CR><LF>
Relocation Offset: ed346000<CR><LF>
Relocation fdt: eb9f8608 - eb9fecd0<CR><LF>
CR: M/C/I<CR><LF>
Using default environment<CR><LF>
<CR><LF>
no mmc device at slot 1<CR><LF>
dwmmc@fe2b0000: 1 (SD), dwmmc@fe2c0000: 2, sdhci@fe310000: 0<CR><LF>
Bootdev(atags): mmc 1<CR><LF>
MMC1: Legacy, 52Mhz<CR><LF>
PartType: EFI<CR><LF>
DM: v1<CR><LF>
No misc partition<CR><LF>
boot mode: None<CR><LF>
FIT: No fdt blob<CR><LF>
Found DTB in boot part<CR><LF>
DTB: rk-kernel.dtb<CR><LF>
HASH(c): OK<CR><LF>
I2c0 speed: 100000Hz<CR><LF>
vsel-gpios- not found! Error: -2<CR><LF>
vdd_cpu init 900000 uV<CR><LF>
PMIC:  RK8090 (on=0x40, off=0x00)<CR><LF>
vdd_logic init 900000 uV<CR><LF>
vdd_gpu init 900000 uV<CR><LF>
vdd_npu init 900000 uV<CR><LF>
io-domain: OK<CR><LF>
Could not find baseparameter partition<CR><LF>
Model: Rockchip RK3568 EVB1 DDR4 V10 Board<CR><LF>
Rockchip UBOOT DRM driver version: v1.0.1<CR><LF>
VOP have 2 active VP<CR><LF>
vp0 have layer nr:3[1 3 5 ], primary plane: 5<CR><LF>
vp1 have layer nr:3[0 2 4 ], primary plane: 4<CR><LF>
vp2 have layer nr:0[], primary plane: 0<CR><LF>
Using display timing dts<CR><LF>
dsi@fe060000:  detailed mode clock 132000 kHz, flags[8000000a]<CR><LF>
    H: 1080 1095 1097 1127<CR><LF>
    V: 1920 1935 1937 1952<CR><LF>
bus_format: 100e<CR><LF>
VOP update mode to: 1080x1920p0, type: MIPI0 for VP1<CR><LF>
VOP VP1 enable Smart0[654x270->654x270@213x825] fmt[2] addr[0xedf04000]<CR><LF>
final DSI-Link bandwidth: 876 Mbps x 4<CR><LF>
PHY is not locked<CR><LF>
generic write fifo is full<CR><LF>
failed to write cmd0: -110<CR><LF>
failed to send on cmds: -110<CR><LF>

[JeffyCN]

those are u-boot logs...
the u-boot's vop display driver might use kernel's dts, so maybe:
1/ something wrong in your u-boot
or
2/ something wrong in your kernel 5.10's dts(related to vop display driver)

[chrisiberg]

@Shaggy013
Thnx a lot!

I only had to patch rk3568-nanopi5-common.dtsi for the correct rootfs

bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 coherent_pool=1m root=PARTUUID=614e0000-0000 rw rootwait";

seems to be ok.
Now I stuck at the correct mali version vor 5.10
g2p0 seems not to work, how can I find out, and where are the correct sources?

[chrisiberg]

@JeffyCN

What is all needed for a hw accelerated chromium in my local.conf?

[chrisiberg]

Thnx!
I'm a big step forward.

chromium 103 is unstable, trying and compiling 105 now.

Is it normal that glmark2-es2-drm is not starting, or is there something missing?

glmark2-es2

arm_release_ver of this libmali is 'g2p0-01eac0', rk_so_ver is '4'.
=======================================================
    glmark2 2021.12
=======================================================
    OpenGL Information
    GL_VENDOR:     ARM
    GL_RENDERER:   Mali-G52
    GL_VERSION:    OpenGL ES 3.2 v1.g2p0-01eac0.327c41db9c110a33ae6f67b4cc0581c7
=======================================================

glmark2-es2-drm

arm_release_ver of this libmali is 'g2p0-01eac0', rk_so_ver is '4'.
Error: eglCreateWindowSurface failed with error: 0x3009
Error: eglCreateWindowSurface failed with error: 0x3009
Error: CanvasGeneric: Invalid EGL state
Error: main: Could not initialize canvas

[JeffyCN]

try:
glmark2/glmark2#177

[chrisiberg]

Chromium is unstable, closing randomly without any useable error, does anybody have an idea?

[JeffyCN]

chromium on wayland is unstable for years, but it's getting better:)