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lemberg's Introduction

Lemberg is a time-predictable VLIW processor optimized for
performance.

Lemberg can execute up to four instructions per cycle in a four-stage
pipeline. The processor includes one to four ALUs, a jump- and a
memory-unit, and optionally also a floating-point unit for single and
double precision floating-point numbers. Instructions are cached in a
method cache, and data may be cached in a stack cache, direct-mapped
cache or a fully associative cache.

Lemberg is time-predictable in the sense that the worst case execution
time of program fragments can be computed easily. The caches have been
designed to reduce the overestimation for worst-case execution time
analysis as much as possible. Branch prediction is optional and was
designed with analyzability in mind.

The processor in its largest configuration runs at 66 MHz on an Altera
DE2-70 board, where it consumes about 45K logic cells and 62KB of
on-chip memory, including the floating-point unit and
caches. Naturally, smaller configurations require fewer resources and
usually can run at higher clock frequencies.

Along with the hardware implementation come an assembler, a back-end
for LLVM, and a basic port of the newlib libc implementation.

lemberg's People

Contributors

jeunes2 avatar schoeberl avatar

Stargazers

Timothy avatar avatar Tingyuan LIANG avatar Qicny avatar V. Lee Horton avatar avatar Howard Mao avatar avatar Stefan Hepp avatar Matthias Blaicher avatar Jeff Bush avatar Farhan Rahman avatar avatar Daniel Wiltsche-Prokesch avatar avatar Sebastien Van Cauwenberghe avatar aoh83 avatar Benedikt Huber avatar Trygve Laugstøl avatar

Watchers

avatar avatar avatar avatar Qicny avatar ju avatar

Forkers

schoeberl rpg-7 qicny kuanwoo zslwyuan mfkiwl orb1t-ua

lemberg's Issues

Disable FPU in compiler

The compiler currently assumes that the FPU is present for both single and double precision. This should be made configurable so the generated code matches the hardware if it does not include an FPU.

System information and timer

There is currently no information about the processor (clock frequency, features, revision number, ...) and no timer.

Stack cache write-back

Write-back (wb.s) is currently not implemented. Stacks that are larger than the stack cache will lead to random crashes.

Interrupts

There is currently no support for interrupts. Injecting an appropriate operation in the inflate stage is probably the least invasive way of interrupt handling within the pipeline.

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