jiteshnayak2004 Goto Github PK

aes-128-sysverilog-riscv

AES-128 block written in SystemVerilog

agrisaathi

arm-soc-design-labs

lab files for arm soc design course

dadda_multiplier

deep-detect

a deepfake detector usign the cnn and lstm architecture

hdl_practice

contains simple basic block implementation in various hdl's

jemu

my attempt to create a RV32I simulator similar to spike

jfpu

floating point unit following the IEEE 754 standard

jiteshnayak2004

Config files for my GitHub profile.

jiteshnayak2004.github.io

personal website

ml_lab

nvim-setup

A launch point for your personal nvim configuration

pd_asic

this is a repo that contains the notes and lab assignments for physical design for ASIC course

pd_openlane

rtl to gds flow using openlane

pesu-io__mlalgo

pygamett

pygame tutorials following corey schafer

router_placement

predicting router position by analyzing wlan throughput

rtl_notes

Notes I made on RTL design and verification. Currently has verilog, system verilog and formal verification notes

rvxcellerate

single cycle risc-v core implementation

silent_room-hack

grc files for gnu radio used in the silent room hackathon

socketfilexfer

a file transfer cli to share files b/w two devices using socket programming

sv_tutorials

SystemVerilog Tutorial

synapse_proj

Detecting real time violence using computer vision and ml

systemverilog-playground

Various basic topics for SystemVerilog Modules

uart

uart protocol implementation in systemverilog

word-rush

an addictive mini game inspired from wordle