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2020_ti_competion_question_a

2020电赛A题代码整理

30daymakeos

《30天自制操作系统》源码中文版。自己制作一个操作系统（OSASK）的过程

8051

8051 core

accelerating-cnn-with-fpga

This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.

adafruit_ads1x15

Driver for TI's ADS1015: 12-bit Differential or Single-Ended ADC with PGA and Comparator

adcs

ADC采集项目： 1. 百片多通道ADC采集，大数据量缓存，USB3.0数据上传 难度指数：★★★★☆ 2. 高速低精度、低速高精度ADC信号采集，USB2.0数据上传 难度指数：★★★☆☆

ahb-to-apb-bridge-rtl-design-using-verilog-hdl

amba4-apb

Advanced Pheripheral Bus design using verilog HDL

apb-verification

verification of APB bus on System Verilog. creating a testbench consisting of modules to check and improve the functional coverage.

arm_amba_design

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

awesome-books

160+ 本技术类精华电子书开源了，免费下载，包括 前端、后端、数据结构与算法、计算机基础、设计模式、数据库等书籍

aws-fpga

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

biriscv

32-bit Superscalar RISC-V CPU

chinese-translation-of-pci-express-technology-

Chinese Translation on <PCI Express Technology Comprehensive Guide to Generations 1.x, 2.x and 3.0> by Mindshare Mindshare

cnn-on-fpga

FPGA

cnn_accelerator

【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器

cores

Various HDL (Verilog) IP Cores

design-and-verification-of-apb-protocol-using-uvm

APB Protocol is designed and verified using System Verilog based UVM. The tool used in designing and simulation is EDA Playground.

dic-approximateaverage

digital-design-lab

digital_ic_design_notes

数字IC设计 学习笔记

e200_opensource

The Ultra-Low Power RISC Core

exercise

exercise for nndl

floating-point-addition

使用Verilog设计的带四舍五入功能的浮点加法器

fpga

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga-1

FPGA

fpga-ftdi245fifo

FPGA-based USB fast data transmission using FT232H/FT600 chip. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。

fpga-proj

FPGA project

fpga-zynq

Support for Rocket Chip on Zynq FPGAs

fucking-algorithm

刷算法全靠套路，认准 labuladong 就够了！English version supported! Crack LeetCode, not only how, but also why.