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juju994's Projects

autox icon autox

A UiAutomator on android, does not need root access(安卓平台上的JavaScript自动化工具)

cacti icon cacti

An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model

cacti-3dd icon cacti-3dd

This is the working cacti 3DD simulator implementation with changes for proper working for all config files. Read README ALTERED for more information regarding the changes done.

destiny_3d_cache icon destiny_3d_cache

Source code for DESTINY, a tool for modeling 2D and 3D caches designed with SRAM, eDRAM, STT-RAM, ReRAM and PCM. This is mirror of following repository:

dramsim3 icon dramsim3

DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator

gem5_dramsim3 icon gem5_dramsim3

This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.

gpt_academic icon gpt_academic

为ChatGPT/GLM提供图形交互界面，特别优化论文阅读/润色/写作体验，模块化设计，支持自定义快捷按钮&函数插件，支持Python和C++等项目剖析&自译解功能，PDF/LaTex论文翻译&总结功能，支持并行问询多种LLM模型，支持清华chatglm2等本地模型。兼容复旦MOSS, llama2, rwkv, newbing, claude, claude2等

nvmexplorer icon nvmexplorer

https://nvmexplorer.seas.harvard.edu NVMExplorer is a cross-stack design space exploration framework for evaluating and comparing on-chip memory solutions including emerging, embedded non-volatile memories.

nvsim icon nvsim

NVSim - A performance, energy and area estimation tool for non-volatile memory (NVM)

ramulator icon ramulator

A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf

ramulator2 icon ramulator2

Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf

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