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berkeley-hardfloat-chisel3

Hardfloat using chisel3

bragghls

PyTorch model to RTL flow for low latency inference

caravel_user_project

https://caravel-user-project.readthedocs.io

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chisel-de1soc-fpga-template

A template Chisel project for the DE1SOC FPGA board

chisel-matmul

chisel-testutil

utility for test driver

chiseltest

The official testing library for Chisel circuits.

clwrap

A convenient C++ wrapper class for OpenCL host codes

codes

The Co-Design of Exascale Storage Architectures (CODES) simulation framework builds upon the ROSS parallel discrete event simulation engine to provide high-performance simulation utilities and models for building scalable distributed systems simulations

firemarshal

Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.

gds3d

groqflow

GroqFlow provides an automated tool flow for compiling machine learning and linear algebra workloads into Groq programs and executing those programs on GroqChip™ processors.

groqsnips

This repository includes my groq snippets for learning, testing and benchmarking purposes.

hacogen

Stream compressor generator framework written in Chisel3

idbench

indirect memory access benchmark

intel-fpga-opencl-rtl

Intel FPGA OpenCL RTL library examples

jlesc.github.io

Source repository for the JLESC website. Please read https://github.com/JLESC/jlesc.github.io/wiki for instructions!

kernels

This is a set of simple programs that can be used to explore the features of a parallel platform.

kzt-image-tools

just a collection of small tools for manipulating and analyzing images (e.g., PSNR, compression ratio, filters)

lwc_crypto_iot

pca-comp-precision-analysis

riscv-tools

RISC-V Tools (ISA Simulator and Tests)

thapi