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10g-low-latency-ethernet

10G Low Latency Ethernet

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

axi_node

AXI X-Bar

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

cocotb-coverage

Functional Coverage and Constrained Randomization Extensions for Cocotb

cocotbext-axi

AXI interface modules for Cocotb

cocotbext-pcie

PCI express simulation framework for Cocotb

easieruvm

DOULOS Easier UVM Code Generator

gen_amba

AMBA bus generator including AXI, AHB, and APB

gen_uvm

EasierUVM from Doulos now written in Python for easier UVM with framework and template generator

go

The Go programming language

isp_uvm

A Framework for Design and Verification of Image Processing Applications using UVM

iverilog

Icarus Verilog

openisp

Image Signal Processor

peakrdl

Control and status register code generator toolchain

peakrdl-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

peakrdl-uvm

Generate UVM register model from compiled SystemRDL input

pyuvm

The UVM written in Python

react-flow

Highly customizable library for building interactive node-based UIs, editors, flow charts and diagrams

streambenchmark.jl

A version of the STREAM benchmark which measures the sustainable memory bandwidth.

systemrdl-compiler

SystemRDL 2.0 language compiler front-end

usb-test-suite-build

Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores

usb20

usb20dev

USB 2.0 FS Device controller IP core written in SystemVerilog

uvm-python

UVM 1.2 port to Python

uvm_axi

uvm AXI BFM(bus functional model)

uvmprimer

Contains the code examples from The UVM Primer Book sorted by chapters.

verilator

Verilator open-source SystemVerilog simulator and lint system

verilog-axi

Verilog AXI components for FPGA implementation

xkisp

xkISP：Xinkai ISP IP Core (HLS)