Name: Lazar Vulic
Type: User
Company: Faculty of Electrical Engineering
Bio: BSc in Computer Engineering and Information Theory. MSc student, Software Engineering, at School of Electrical Engineering, University of Belgrade.
Twitter: BoyHeaviside
Location: Belgrade, Serbia
Lazar Vulic's Projects
Simple assembler functionalities
Some network monitoring concepts
SQL Queries implemented using Java
Preemptive, multithread operational system. System that supports Thread, Semaphore and Event concept. Eclipse IDE and Borland C++ 3.1 compiler for 8086 were used.
Config files for my GitHub profile.
A compiler for MicroJava. Lexical analysis with syntax and semantical error catching. Bytecode generating for MJ virtual machine.
JAVA games with GUI and Threads Concept
Rolling the Dice console game
Application written in Java using Sping, Thymeleaf and H2 database in collaboration with ETF and Zühlke Serbia. SQL Injection, XSS, CSRF attacks and prevention. Static analysis using SonarQube, dynamic analysis using OWASP ZAP. Implemented authorization and authentication using TOTP authenticator. DevOps - concepts of logging and auditing.
Some simple filters implementation for data signal proccessing and others
Implementation of simple STM32F103x6 microcontroller using multiple environments
Simple register realisation for SystemVerilog Verification
Simple Web application for creating hotel reservations, only fronted implemented
Simple Tic-Tac-Toe game written in Java using Java AWT Events, Java Util and Java Swing
Web app for Tokyo 2021 Olympics Games (complete players medal statistics, players from all countries, all sports and disciplines, tournaments making...) Implemented using multiple programming techniques.
Output .o file in structure similar to one in ELF is made from one input .s file in assembly language similar to x86. Two or more .o files will be merged in one .hex file, that will be the input file for our emulator. Emulator will execute .hex file and the output will be shown in console.
UI/UX for Zoo Park in Belgrade, made with Figma. Documentation provided.
Simple module realisation for Verilog Synthesis
Simple module realisation for Verilog Simulation